EDA Flow and Logic Synthesis Engineer — Senior Engineer

Job Title

EDA Flow and Logic Synthesis Engineer — Senior Engineer

Role Summary

Work on mid-end ASIC/IP flows that convert RTL into implementation-ready inputs for physical design. The team builds automation, quality checks, and flows for synthesis, DFT, static checking, formal equivalence, and power analysis to support scalable IP delivery.

The role focuses on flow development, automation (Tcl), AI-assisted analysis, debugging failures across teams, and improving handoff quality and documentation.

Experience Level

Senior — the title is senior-level. The posting cites typical experience of 2+ years in relevant ASIC/mid-end flow work or equivalent project experience.

Responsibilities

Primary responsibilities include running, improving, and supporting mid-end flows and ensuring clean handoffs to implementation.

• Develop, run, and support mid-end flows for synthesis, DFT, static checking, formal equivalence, power analysis, and quality gates.
• Convert RTL outputs into clean, constrained, implementation-ready inputs for physical design teams.
• Build and maintain Tcl-based automation, dashboards, and project infrastructure.
• Apply AI tools to accelerate debugging, triage flow logs, summarize QoR trends, and assist script development/refactoring.
• Debug flow failures end-to-end: analyze reports, isolate root causes, and drive resolution with design, verification, DFT, and implementation teams.
• Improve documentation, handoff criteria, and reusable collateral to ensure consistent execution across IP programs.

Requirements

Must-have technical skills and experience for immediate contribution.

• Working knowledge of ASIC design, verification, and mid-end development flows; practical experience with synthesis and resolving synthesis issues.
• Practical Tcl scripting skills and automation-first mindset.
• Familiarity with one or more of: DFT concepts, static checking (SpyGlass or equivalent), formal equivalence (e.g., Formality), or power analysis, with willingness to expand skills.
• Ability to use AI tools effectively to speed debugging, summarize results, and improve scripts and flows.
• Strong analytical, problem-solving, communication, and documentation skills; ability to collaborate across RTL, verification, DFT, and implementation teams.

Nice-to-have:

• Experience across the full mid-end toolset: DFT, SpyGlass, Formality, and power analysis.
• Experience with IP development methodologies, IP packaging, or reusable IP delivery/release collateral.
• Hands-on experience with Synopsys tools such as Fusion Compiler and VC SpyGlass.

Education Requirements

BS or MS in Electrical Engineering or Computer Engineering is specified; the posting also allows equivalent practical experience in lieu of degree.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.