DV Power Vectors & Window Extraction Engineer (Staff/Sr Staff)

Job Title

DV Power Vectors & Window Extraction Engineer (Staff/Sr Staff)

Role Summary

Engineer responsible for developing and executing design-verification (DV) power vectors and extracting power-analysis windows across simulation, emulation, and silicon-validation flows. Works with DV, design, power, physical design, emulation, and post-silicon teams to validate power behavior and enable pre-/post-silicon correlation.

Experience Level

Senior-level role. Prefer candidates with approximately 7–15 years of experience in design verification, power-aware verification, vector development, or power analysis.

Responsibilities

The core responsibilities include building and maintaining verification assets and deriving meaningful power-analysis windows:

• Develop and execute DV power vectors for workloads, power states, transitions, boot flows, retention, reset, and stress scenarios.
• Bring up and maintain simulation, emulation, and power-aware verification environments.
• Analyze waveforms, activity dumps, power reports, and execution logs to identify power-analysis windows.
• Extract and document windows for peak/average power, dynamic voltage drop, thermal analysis, and pre-/post-silicon correlation.
• Debug vector failures, power-state sequencing issues, waveform mismatches, and unexpected power behavior.
• Maintain traceability between test cases, configurations, waveforms, extracted windows, and delivered vector collateral.
• Collaborate closely with cross-functional teams (DV, Design, Power, Physical Design, Emulation, PTE, Post-Silicon).

Requirements

Must-have technical skills and experience:

Must-have:

• 7–15 years experience in design verification, power-aware verification, vector development, or power analysis.
• Strong understanding of RTL simulation and waveform analysis.
• Familiarity with SystemVerilog/UVM or equivalent verification environments.
• Knowledge of low-power concepts: power states, clock gating, retention, and isolation.
• Experience with simulation, emulation, GLS, or silicon-validation flows and power estimation/activity analysis.
• Proficiency with scripting (Python, Perl, Shell, or Tcl).
• Experience using waveform-debug and power-analysis tools and identifying representative/peak/corner-case power windows.
• Strong debugging, analytical, documentation, and cross-team communication skills.

Nice-to-have:

• Experience with UPF and power-intent verification.
• Knowledge of CPU, SoC, memory, interconnect, or subsystem power behavior.
• Experience with dynamic voltage drop, IR-drop, VMIN, or thermal analysis.
• Familiarity with emulation platforms and large-scale workload execution.
• Experience correlating pre-silicon power results with post-silicon measurements and understanding frequency-voltage operating points.

Education Requirements

Bachelor's, Master’s, or PhD in Computer Science, Electrical/Electronics Engineering, Computer Engineering, Engineering, or a related technical field. The posting lists degree-plus-experience options: Bachelor's + 4+ years, Master's + 3+ years, or PhD + 2+ years of relevant hardware/verification experience (equivalent practical experience implied where applicable).

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.