DV Engineer

Job Title

DV Engineer

Role Summary

Responsible for functional verification of DSP blocks and related IP within Broadcom's semiconductor designs. Work within a verification team to develop testbenches, create verification plans, and ensure design quality through simulation and debug.

Experience Level

Mid-level. Years of experience not specified in the posting.

Responsibilities

Primary responsibilities include:

• Develop and implement verification plans and testbenches for DSP and related IP.
• Create and run simulations, analyze results, and debug RTL and verification issues.
• Work with design and SoC teams to integrate and validate verification environments.
• Contribute to coverage-driven verification and maintain verification infrastructure and documentation.

Requirements

Core qualifications and skills expected:

• Experience in digital verification methodologies and environments (for example UVM/SystemVerilog) — specific tools and years not specified in the posting.
• Strong debugging and simulation skills; familiarity with DSP verification preferred.
• Good collaboration and communication skills and the ability to document verification results.

Nice-to-have: experience with scripting (Python/Tcl/Perl), emulation, or FPGA prototyping — not specified as required.

Education Requirements

Not specified.

About the Company

Company: Broadcom

Headquarters: Irvine, California, United States

Broadcom is a global technology leader that designs, develops, and supplies a wide range of semiconductor and infrastructure software solutions. The company is known for its innovations in wireless and broadband communications, enabling a connected world.