DSP / NPU Design Verification Sr Staff Engineer

Job Title

DSP / NPU Design Verification Sr Staff Engineer

Role Summary

Lead verification engineer responsible for planning and executing design verification for high-performance DSP and NPU IP used in SoCs. Collaborate with architecture, implementation, power, post-silicon and backend teams to deliver silicon-quality verification.

Work focuses on building robust, automated SystemVerilog/UVM environments, driving coverage, and debugging IP, subsystem and SoC-level failures.

Experience Level

Senior - the posting specifies 12+ years of processor/ASIC design verification experience for this role.

Responsibilities

Core responsibilities include ownership of verification architecture, execution, and delivery for DSP/NPU IP.

• Drive design verification with cross-functional teams (architecture, implementation, power, post-silicon, backend).
• Design and implement SystemVerilog/UVM testbench architecture and verification environments; develop test plans.
• Develop and deploy verification methodologies and automation to improve quality and efficiency.
• Perform simulations and debug failures at IP, subsystem and SoC levels; support gate-level and timing-annotated simulations.
• Execute power-aware RTL verification and gate-level simulation.
• Use assertions, formal checks, HW-SW co-verification, simulation acceleration and emulation as required.
• Meet coverage goals and ensure verification completeness for product release.

Requirements

Must-have and preferred skills for successful performance in this role.

• 12+ years experience in processor/ASIC design verification with strong digital design and processor architecture knowledge.
• Expertise in SystemVerilog and UVM testbench architecture and implementation.
• Experience with simulators from Synopsys, Mentor or Cadence and gate-level simulation (timing-annotated, power-aware).
• Proficiency in scripting and automation (Perl, Python, Shell, Makefile) and strong analytical/debugging skills.
• Familiarity with power-aware flows (UPF) and assertions/formal verification techniques is a plus.
• Experience writing C- and assembly-level testcases is preferred.
• Knowledge of SystemC and HDLs (Verilog, SystemVerilog) and experience verifying processor subsystems are preferred.
• Experience creating validation suites and building automation frameworks.
• Excellent interpersonal and communication skills.

Education Requirements

Degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related technical field. The posting lists degree/experience equivalents: Bachelors + 6+ years, Masters + 5+ years, or PhD + 4+ years of relevant hardware engineering experience.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.