DRAM Memory Design Engineer - Principal (MTS / SMTS)

Job Title

DRAM Memory Design Engineer - Principal (MTS / SMTS)

Role Summary

Senior semiconductor design engineer responsible for designing and optimizing next-generation DRAM circuits and subsystems. The role partners with global design, verification, layout, and multi-functional teams to deliver high-performance, reliable memory products.

Primary focus areas include circuit development, simulation, silicon validation, and mentoring/technical leadership within the DRAM engineering organization. This position is onsite at the Boise, ID main site.

Experience Level

Senior-level. Typical experience expectations: senior technical staff (SMTS) candidates often have 15+ years; equivalent senior requirements described as ~10+ to 15+ years depending on formal degree and background.

Responsibilities

The role leads circuit-level design and validation activities for DRAM products and contributes to technical direction and mentoring.

• Design and optimize digital and analog circuits including memory arrays, control logic, datapaths, address decoding, and I/O circuitry.
• Lead circuit development, simulation, verification, and silicon validation to meet performance, power, area, and quality targets.
• Drive floor-planning, layout optimization, parasitic analysis, and tape-out activities.
• Advance AI-assisted design, automation, and design-space exploration in collaboration with internal and external partners.
• Provide technical leadership, innovation, cross-functional coordination, and mentorship of engineers.

Requirements

Must-have technical skills and capabilities for effective performance in this role.

• Extensive knowledge of CMOS circuit design, device behavior, and state-machine logic.
• Experience with Verilog modeling and industry-standard circuit/signal simulation tools.
• Experience with power delivery network (PDN) analysis and silicon-validation activities.
• Proficiency in scripting for automation (Python, Tcl, Perl or similar).
• Familiarity with layout-related concerns: parasitic analysis, floor-planning, and tape-out processes.
• Strong analytical and problem-solving skills, effective written and verbal communication, and proven cross-functional collaboration.
• Demonstrated ability to lead complex circuit design projects and mentor other engineers.
• Nice-to-have: experience with DDR5/LPDDR/GDDR/HBM memory technologies, FINESIM/HSPICE, and AI/ML-assisted design flows or advanced design automation frameworks.

Education Requirements

Bachelor's degree in Electrical Engineering or related field is indicated; employers list combinations such as M.S.E.E. with ~10+ years, B.S.E.E. with ~12+ years, or equivalent relevant semiconductor design experience. SMTS-level candidates typically have ~15+ years. Preferred: Master's or PhD in Electrical Engineering or related discipline. Equivalent practical experience is accepted.

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.