Distinguished Engineer, Chiplet Lead - Photonic Fabric

Job Title

Distinguished Engineer, Chiplet Lead - Photonic Fabric

Role Summary

Lead the end-to-end development of a heterogeneous photonic chiplet that integrates a high-speed electrical IC (with analog SERDES) and a photonic integrated circuit (PIC) using advanced co-packaging technologies. Act as the single technical owner across die, package, optics, firmware, and system boundaries and drive delivery from concept through silicon bring-up, ATE, and system validation.

Experience Level

Senior-level role. Typical experience: 15+ years of relevant industry experience, or 8–12 years with an advanced degree as described in the Education Requirements.

Responsibilities

Primary responsibilities include

• Own product design across Electrical IC, Photonic IC, firmware, and advanced packaging.
• Lead micro-architecture and RTL development for electrical ICs including high-speed SERDES and digital subsystems.
• Collaborate with verification teams for digital RTL, AMS, and electrical-optical interface verification.
• Work with physical design and packaging teams on floorplanning, timing, power, and physical verification closure.
• Define and drive DFT strategy for digital, analog SERDES, and system-level testability.
• Partner with photonics engineering on PIC architecture, interfaces, and electrical–optical co-design.
• Coordinate with test engineering to enable ATE, develop test programs, and support debug.
• Lead system-level validation across boards, optics, firmware, and software; perform cross-domain root-cause analysis.
• Mentor senior engineers and influence cross-functional teams in a matrixed organization; report technical status and risks to product and engineering leadership.

Requirements

Must-have skills and experience:

• Extensive ASIC/SoC development experience with end-to-end chip ownership.
• Strong background in micro-architecture and RTL design.
• Deep experience with high-speed analog SERDES and related analog/mixed-signal tradeoffs.
• Experience with physical design, sign-off, timing and power closure.
• DFT and manufacturing test experience, including system-level testability considerations.
• Advanced packaging and chiplet-style integration experience; post-silicon bring-up and ATE familiarity.
• Proven ability to articulate architectural and implementation tradeoffs across performance, power, area, yield, cost, schedule, and risk.
• Track record of driving alignment across cross-functional teams and communicating technical status to executive leadership.

Nice-to-have:

• Prior delivery of high-speed I/O and/or optical products to production.
• Prior experience as a Chip Lead, SoC Architect, or system-level technical lead.

Education Requirements

Bachelor's degree in Computer Science, Electrical Engineering, or a related field (with 15+ years of experience), OR Master’s degree or PhD in Computer Science, Electrical Engineering, or related fields with approximately 8–12 years of experience. Equivalent practical experience may be acceptable where explicitly stated by the employer.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.