Display Synthesis Engineer, Sr Lead
QualcommJob Title
Display Synthesis Engineer, Sr Lead
Role Summary
Lead a synthesis/implementation team for the Display sub-system, owning signoff-quality synthesis, timing and low-power constraints, and delivery of netlists for silicon implementation. Work closely with design, DFT and physical-design teams to meet area, power and performance targets.
Experience Level
Senior role — expects an experienced engineer with leadership responsibilities. Typical profile: 5+ years in synthesis/implementation or related hardware engineering (see education section for minimum degree/experience combinations).
Responsibilities
Key responsibilities include:
- Lead and mentor a team executing synthesis and implementation for Display subsystems.
- Develop and deliver signoff-quality synthesis and timing constraints for complex, multi-clock-domain blocks.
- Implement low-power intent (UPF) and optimize flows for area, power and performance.
- Run and analyze flows: synthesis (Genus/DCG/Fusion), STA (PrimeTime), LEC/low-power checks (Cadence Conformal), MEMBIST, RTL lint and DFT/DRC.
- Develop and maintain TCL/Perl/Python scripts to automate flows, debug results, and support ECOs.
- Collaborate with RTL, DFT and physical-design teams to validate constraints, deliver netlists, and support timing closure.
- Handle ECOs, formal verification tasks, and maintain high quality metrics across projects.
- Manage multiple concurrent, time-critical projects and improve execution efficiency.
Requirements
Must-have technical skills and experience:
- Hands-on experience with Synopsys Genus/DCG/Fusion Compiler for synthesis.
- Hands-on experience with Synopsys PrimeTime for STA and timing closure on multi-clock-domain designs.
- Experience with Cadence Conformal LEC and Conformal Low Power; UPF-based low-power implementation.
- Experience writing and validating timing constraints and implementing MCMM synthesis and optimization.
- Experience with memory BIST insertion, RTL lint, DFT flows and DRC checks.
- Scripting experience (TCL, Perl, Python) for flow automation and troubleshooting.
- Proven ability to lead teams, communicate with stakeholders, and coordinate cross-functional execution.
- Ability to handle ECOs and formal verification activities.
Nice-to-have:
- Experience in RTL development or physical design.
- Experience with additional power-optimization techniques such as clock gating.
Education Requirements
Bachelor's, Master’s or PhD in Computer Science, Electrical/Electronics Engineering, Engineering or a related field. Minimum experience alternatives stated in the posting: Bachelor's +3 years, Master's +2 years, or PhD +1 year of relevant hardware engineering experience. Equivalent practical experience may be considered.
About the Company
Company: Qualcomm
Headquarters: San Diego, California, United States
Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.
