Director - STA

Job Title

Director - STA

Role Summary

Manage a team of static timing analysis (STA) engineers working on advanced-node AI, edge, and automotive MPU SoCs. Responsible for timing analysis, constraint development, subsystem and full-chip timing closure, and setting technical direction for the STA organization.

Work cross-functionally with architecture, RTL, physical design, methodology, verification, and EDA vendors to deliver complex SoC projects on schedule and improve STA flows and methodology.

Experience Level

Senior - 15+ years of experience in Physical Design for complex SoCs; at least 3 years in STA lead roles.

Responsibilities

The role combines technical leadership, hands-on STA work, and cross-functional coordination.

• Lead and mentor an STA team delivering timing closure for MPU SoCs across modes and scenarios.
• Develop, implement, and verify STA constraints and timing checks at subsystem and SoC level.
• Drive timing closure activity including floor-planning, placement, clocking, and P&R coordination.
• Collaborate with Architecture and RTL teams to influence early design decisions and timing fixes.
• Coordinate with RTL, DV, DFT, EDA vendors, and DTCO teams to resolve timing and implementation issues.
• Improve STA flows, methodology, and automation; adopt new techniques and AI tools where beneficial.
• Manage multi-site execution and schedule delivery across global design teams.

Requirements

Must-have technical experience and capabilities. Education requirements are listed separately below.

• 15+ years of experience in Physical Design for complex SoCs.
• 3+ years in STA lead or management roles with proven delivery of timing closure.
• Deep expertise in constraint development, timing verification, and full-chip timing closure.
• Strong knowledge of Physical Design practices: floor-planning, placement, clocking, P&R coordination.
• Familiarity with RTL and basic Verilog to collaborate on timing fixes.
• Experience with advanced timing topics: crosstalk, noise, on-chip variation (OCV), timing margins, jitter, IR drop, and spice analysis.
• Experience coordinating with EDA vendors and multi-discipline SoC teams (DV, DFT, DTCO).
• Excellent oral and written communication skills and ability to set technical direction.
• Ability to drive methodology and flow improvements and to adopt AI/automation in STA workflows.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering or Computer Engineering.

About the Company

Company: NXP Semiconductors

Headquarters: Nijmegen, Netherlands

NXP Semiconductors N.V. is a global semiconductor company that provides High Performance Mixed Signal and Standard Product solutions. With over 45,000 employees and operations in more than 35 countries, NXP is a leader in secure connectivity solutions for embedded applications, catering to automotive, industrial IoT, mobile, and communication infrastructure markets. The company is committed to innovation and sustainability, advancing a smarter, safer, and more sustainable world through technology.