Director - Silicon Logical Design
Axelera AIJob Title
Director - Silicon Logical Design
Role Summary
Lead and scale Axelera AI's digital (logical) design organization for AI accelerator SoCs. Responsible for architectural realization, RTL implementation, integration, and delivery from specification through tape-out across multiple silicon programs.
This is a hands-on leadership role combining technical execution, cross-discipline coordination, and team development in a fast-paced startup environment.
Experience Level
Senior — Director-level. The posting does not state a formal number of years, but the role requires extensive experience in complex SoC digital design and multiple tape-outs.
Responsibilities
Lead technical execution and build the logical design capability across projects.
- Recruit, lead, and mentor RTL and integration engineers; define team structure and processes.
- Translate system and micro-architecture specifications into high-quality RTL (SystemVerilog/Verilog).
- Own end-to-end logical design delivery for one or more SoCs from concept through tape-out.
- Define and enforce RTL quality, coding standards, reuse, and design reviews.
- Oversee block- and top-level integration to meet performance, power, area, and schedule targets.
- Collaborate with architecture, verification, physical design, DFT, software, and product teams to achieve functional and timing closure.
- Support silicon bring-up, debug, validation, and root-cause analysis of silicon issues.
- Contribute to long-term IP strategy, technology roadmap, and architecture directions.
Requirements
Must-have technical skills and leadership experience; preferred items listed separately.
- Extensive experience in digital/logical design of complex SoCs with multiple successful tape-outs.
- Proven ability to lead and grow high-performing silicon design teams.
- Strong RTL and micro-architecture expertise (SystemVerilog / Verilog).
- Experience with large-scale SoC integration (CPUs, accelerators, memory subsystems, interconnects).
- Understanding of performance, power, and area trade-offs at advanced process nodes.
- Experience collaborating with verification and physical design teams to reach functional and timing closure.
- Strong communication skills and ability to operate at both strategic and hands-on technical levels.
Nice-to-have:
- Experience with AI/ML accelerators, GPUs, NPUs, or high-performance compute architectures.
- Familiarity with interconnects (e.g., AXI, NoC), low-power design, multi-clock/multi-voltage systems.
- Silicon bring-up, post-silicon debug, and root-cause analysis experience.
- Experience in startups or fast-scaling environments.
Education Requirements
The posting does not specify a required degree or field. It does note that the company team includes many PhDs (49+), but no formal education requirement or specific fields of study are listed.
About the Company
Company: Axelera AI
Headquarters: Eindhoven, Netherlands
Deep-tech startup developing a next-generation AI platform (Metis™) and AI accelerators/in-memory compute SoCs. The company has raised $120M, employs around 220 people across multiple countries, and operates European offices while focusing on high-performance AI hardware and software.
