Director - Silicon Logical Design

Job Title

Director - Silicon Logical Design

Role Summary

Lead and scale the digital/logical design organization responsible for RTL implementation, integration, and architectural realization of AI accelerator SoCs from specification through tape-out. This is a hands-on leadership role combining technical ownership and people management across multiple silicon programs.

Experience Level

Senior-level. The role expects extensive experience in digital/RTL design, SoC integration and multiple successful tape-outs; no explicit years-of-experience stated.

Responsibilities

Accountable for delivery, quality and team development across logical design activities for one or more SoCs.

• Lead and grow the digital/logical design team (RTL, integration, design methodology).
• Translate system and micro-architecture specifications into high-quality RTL implementations.
• Own end-to-end logical design execution from concept through tape-out.
• Partner with architecture, verification, physical design, DFT, software and product teams to ensure robust designs and schedule adherence.
• Define and enforce RTL quality standards, coding practices, reuse strategy and design reviews.
• Oversee block-level and top-level integration to meet performance, power, area and schedule targets.
• Support silicon bring-up, post-silicon debug and root-cause analysis.
• Contribute to long-term IP strategy, technology roadmap and architecture directions.
• Mentor engineers and foster a culture of technical excellence and ownership.

Requirements

Clear distinction between required qualifications and preferred skills.

• Must-have:
  • Extensive experience in digital/logical design for complex SoCs with multiple successful tape-outs.
  • Proven leadership experience building and scaling high-performing silicon design teams.
  • Strong RTL and micro-architecture expertise (SystemVerilog/Verilog).
  • Experience with large-scale SoC integration (CPUs, accelerators, memory subsystems, interconnects).
  • Solid understanding of performance, power and area trade-offs at advanced nodes.
  • Experience collaborating with verification and physical design teams to achieve functional and timing closure.
  • Strong communication skills and ability to operate at both strategic and hands-on technical levels.
• Nice-to-have:
  • Experience with AI/ML accelerators, GPUs, NPUs or high-performance compute architectures.
  • Familiarity with interconnects (e.g., AXI, NoC architectures), low-power design techniques, and multi-clock/multi-voltage systems.
  • Experience with silicon bring-up, post-silicon debug and root-cause analysis.
  • Experience in startup or fast-scaling environments.

Education Requirements

The posting does not state a required degree or specific field-of-study for applicants. The company description references a team that includes many PhDs, but the role emphasizes extensive practical experience (multiple tape-outs) and demonstrated technical leadership rather than a stated degree requirement.

About the Company

Company: Axelera AI

Headquarters: Eindhoven, Netherlands

Deep-tech startup developing a next-generation AI platform (Metis™) and AI accelerators/in-memory compute SoCs. The company has raised $120M, employs around 220 people across multiple countries, and operates European offices while focusing on high-performance AI hardware and software.