Director Engineering

Job Title

Director Engineering

Role Summary

Lead and grow RTL and design verification (DV) teams to deliver large system-on-chip (SoC) products in Marvell's compute and custom solutions organization. The role owns architecture and verification strategy, execution of SoC development, cross-functional coordination with IP vendors, physical design, and software teams, and drives pre- and post-silicon validation.

Work focuses on high-performance data processing and accelerator platforms with an emphasis on networking and SoC verification at scale.

Experience Level

Senior level. The posting indicates senior leadership experience is required; see Education Requirements for explicit years-of-experience guidance tied to degree level.

Responsibilities

Accountable for technical leadership, SoC verification strategy, and delivery of complex SoC products.

• Build and lead RTL and DV teams; recruit, mentor, and manage engineering staff.
• Define product strategy and requirements for CCS (compute and custom solutions) products with stakeholders.
• Lead RTL and DV efforts for blocks, subsystems, and top-level verification; develop UVM-based environments.
• Define subsystem architecture, micro-architecture, and register specifications; participate in specification write-ups and reviews.
• Conduct performance, architectural and design reviews with cross-functional teams, IP vendors, and customers.
• Coordinate with third-party IP vendors to define customizations and integrations (controllers, PHYs, etc.).
• Collaborate with physical design teams on floorplanning, power analysis, synthesis, and timing signoff.
• Oversee pre-silicon verification: test plans, coverage analysis, full-chip simulation, emulation, performance and power analysis, and debug.
• Support post-silicon bring-up and software integration for prototype tuning and validation.
• Maintain regression suites, debug failures, analyze coverage, and drive verification to meet coverage and closure targets.
• Promote and improve design and verification methodologies and introduce automation to achieve design closure.

Requirements

Core technical skills, leadership experience, and domain knowledge required to lead SoC verification and emulation efforts.

Must-have:

• Proven experience managing technical teams and leading cross-functional engineering efforts for design, emulation, and verification.
• Substantial experience with emulation platforms and building complex SoC emulation models (vendors such as Synopsys, Cadence, Siemens).
• Working knowledge of processor architectures, SoC components, interconnect buses, IO protocols (PCIe, CXL, Ethernet), and memory interfaces (DDR, HBM).
• Strong verification and debug experience on emulation platforms and full-chip verification flows.
• Strong scripting skills (Perl, Python, Tcl, UNIX shell) for automation and verification tasks.

Nice-to-have:

• Experience developing UVM-based verification environments and constrained-random verification methodologies.
• Experience with physical design interactions (floorplanning, power analysis, synthesis, timing closure).
• Domain experience in networking solutions and hardware accelerators.

Education Requirements

Bachelor's degree in Computer Science, Electrical Engineering, or related field with 16+ years of related professional experience; or Master’s degree and/or PhD in Computer Science, Electrical Engineering, or related fields with 12+ years of experience. Equivalent practical experience may be considered where specified.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.