Digital Verification Senior Staff / Principal Engineer

Job Title

Digital Verification Senior Staff / Principal Engineer

Role Summary

Lead the verification effort for complex digital and mixed-signal IP, defining verification strategy, architecture, and methodologies. Serve as the senior technical authority on mission-critical projects and coordinate cross-functional teams to deliver high-quality IP for data center, AI/ML, and 5G applications.

Work within a global engineering team based in Vietnam to drive verification best practices, mentor engineers, and support customer bring-up and debugging.

Experience Level

Senior — requires extensive verification experience; posting specifies 10+ years of experience in design verification.

Responsibilities

The role focuses on technical leadership, verification architecture, and ensuring verification closure and quality across projects.

• Define and review verification strategies, test plans, coverage models, and closure metrics.
• Architect and oversee robust verification environments from functional and micro-architecture specifications.
• Apply advanced verification techniques: constrained random, functional coverage, assertions, and formal methods.
• Lead complex simulation, mixed-signal and real-number modeling, RTL/GLS co-simulation, and debug efforts.
• Develop, standardize, and promote verification methodologies, frameworks, and automation to improve scalability and quality.
• Coordinate cross-functional global teams (Design, DFT, Analog, Software, Validation, Customer) to resolve technical issues and align on decisions.
• Provide final technical sign-off on major design and verification decisions and act as a senior interface for customer support and IP bring-up.
• Mentor and influence engineers at all levels, and lead technical and architectural reviews.

Requirements

Must-have technical skills and competencies; nice-to-have items are indicated.

• Proven expertise in digital design verification methodologies and advanced verification techniques (functional coverage, assertions, constrained random).
• Strong experience with simulation and debug tools (experience specifically cited with VCS/Verdi and formal verification tools).
• Practical experience debugging complex verification environments and root-cause analysis of failing tests.
• Ability to lead technical direction, make risk/quality trade-offs, and drive delivery on schedule for mission-critical projects.
• Excellent English communication skills and demonstrated ability to collaborate with global teams and customers.
• Nice-to-have: knowledge of UPF, UVM, SystemVerilog Assertions (SVA), and experience with Perl/TCL/Python scripting.

Education Requirements

Posting specifies BS, MS, or PhD in Electronics Engineering, Electromechanics, or Telecommunications (degrees in related technical fields or equivalent practical experience implied).

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.