Digital IC Design Intern

Job Title

Digital IC Design Intern

Role Summary

Join the Design-for-Test (DFT) team to support ATPG and scan-based test implementation for complex SoC digital blocks. The role provides hands-on experience implementing test flows, generating and validating test patterns, and working with design, verification and silicon teams to improve testability and debug test-related issues.

Experience Level

Internship level - intended for 2nd or 3rd year undergraduate or early-stage master's students. Entry-level, student-status role.

Responsibilities

Typical responsibilities include:

• Assist with scan insertion and setup of ATPG flows for digital designs.
• Generate and validate test patterns for stuck-at and transition faults.
• Analyze fault coverage and identify coverage gaps or improvements.
• Support silicon bring-up and debug test-related failures.
• Collaborate with IP vendors, design, verification, validation and software teams to resolve testability and verification issues.
• Document test methodologies, results and best practices.

Requirements

Must-have technical skills and attributes:

• Basic understanding of digital logic design and VLSI concepts. (Education details below.)
• Familiarity with scripting languages such as Python, Perl or TCL.
• Strong analytical and problem-solving skills.
• Good communication and teamwork abilities.
• Nice-to-have: exposure to EDA ATPG tools (e.g., Synopsys TetraMAX, Cadence Modus) or similar tools.

Education Requirements

2nd or 3rd year student pursuing a B.Sc. or M.Sc. in Electrical Engineering, Computer Engineering, or a related technical field.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.