Digital Engineer

Job Title

Digital Engineer

Role Summary

Individual contributor responsible for driving RTL-to-GDSII flow, full-chip backend integration, and physical design for complex ASIC/FPGA products. The role sits on the Pune engineering team and focuses on power, signal integrity, physical verification, and tapeout readiness.

Experience Level

Senior-level role. The posting requests 10+ years of relevant experience in backend integration and full-chip physical design.

Responsibilities

The core responsibilities focus on integration, signoff, and methodology improvement.

• Lead full-chip backend integration and physical design activities (floorplanning, power and bump planning).
• Implement and drive RTL-to-GDSII flow for complex designs.
• Perform EM-IR and signal EM analysis; ensure power grid integrity and signoff.
• Run physical verification and signoff checks including DRC, LVS, PERC, ESD, and other tapeout checks.
• Develop and improve design methodologies and automation (scripting) to increase efficiency.
• Collaborate with cross-functional and distributed teams on timing, power, and design optimization.
• Mentor colleagues, teach best practices, and learn FPGA-specific fabric considerations from the team.
• Support tapeout activities and occasionally travel as needed.

Requirements

Key must-have technical skills and expectations.

• Must-have: 10+ years driving backend integration of ASIC blocks and full-chip physical design.
• Must-have: Hands-on experience with industry-standard physical design and verification tools (examples: Innovus, Calibre, Virtuoso, Voltus, Tempus, Conformal).
• Must-have: Strong experience in power and bump planning, EM-IR, signal EM, and power grid integrity analysis and signoff.
• Must-have: Experience performing DRC, LVS, and other signoff checks for tapeout readiness (PERC, ESD, etc.).
• Must-have: Scripting experience (Perl, Python, or similar) for automation and methodology development.
• Must-have: Proven ability to work independently and coordinate with multiple teams across sites/time zones.
• Nice-to-have: Prior experience with highly programmable FPGA fabrics or teaching/adapting ASIC methods to FPGA architectures.

Education Requirements

BS, MS, or PhD in Electronics Engineering, Electrical Engineering, Computer Science, or a closely related technical field — or equivalent practical experience.

About the Company

Company: Lattice Semiconductor

Headquarters: Portland, Oregon, USA

Lattice Semiconductor specializes in low power, small-form-factor programmable logic devices and solutions. The company is known for its innovative technology that enables a wide range of applications, including communication, consumer, and industrial markets.