Skip to main content
Qorvo logo

Digital Design Engineer

Qorvo
September 28, 2026
Full-time
Remote friendly (Chandler, Arizona, United States)
Worldwide
RTL Design Jobs, Level - Entry or Early Career

Job Title

Digital Design Engineer

Role Summary

Design and verify digital control logic for mobile RF products (LNAs, TX controllers, switches) within a mixed-signal semiconductor environment. Work includes RTL design, synthesis, physical implementation, timing closure and verification targeting mobile phone designs.

Role is on-site/hybrid: 3 days in the office and 2 days remote within reasonable commuting distance to the Chandler, AZ office. This position is not eligible for company visa sponsorship.

Experience Level

Professional level. Posting specifies approximately 6 months of relevant experience (or equivalent internship/co-op/graduate credit) as the minimum.

Responsibilities

Primary technical responsibilities include design, implementation and verification tasks:

  • RTL design in Verilog/SystemVerilog for digital control logic and interfaces.
  • Create and run verification test benches; perform simulation-based verification using tools such as Xcelium.
  • Develop timing constraints and synthesis scripts (TCL); perform digital synthesis with Cadence Genus or Synopsys Design Compiler.
  • Perform physical implementation and timing closure using Cadence Innovus, including TCL-based setup scripts and fixing setup/hold/width violations.
  • Participate in RTL-to-GDS flow, area optimization, and DRC/LVS error resolution.
  • Develop automation and flow scripts using Python and other scripting languages to support design and verification tasks.

Requirements

Key required skills and experience (must-haves first):

  • Practical experience with Verilog/SystemVerilog design and verification methodologies.
  • Hands-on experience with Cadence Innovus for physical design and timing closure.
  • Experience with digital synthesis tools (Cadence Genus or Synopsys Design Compiler) and creating timing constraints in TCL.
  • Experience creating verification test benches and running simulations (e.g., Xcelium) to validate RTL.
  • Familiarity with RTL-to-GDS flow, area optimization techniques, and resolving DRC/LVS issues.
  • Proficient in Python scripting for automation; familiarity with other scripting languages is a plus.

Education Requirements

Master's degree in Electrical Engineering is specified. The posting also accepts an internship, co-op, 6 months of relevant experience, or 6 graduate credit hours as meeting the education/experience requirement.


About the Company

Company: Qorvo

Headquarters: Greensboro, NC, US

Qorvo supplies innovative semiconductor solutions that enhance connectivity and power for a variety of applications, including consumer electronics, automotive, and healthcare. With a focus on RF and power solutions, Qorvo combines technology leadership and global manufacturing to address complex challenges in fast-growing industries. Their commitment to excellence and innovation drives them to shape the future of wireless communications.

Qorvo logo

Date Posted: 2026-09-25