Digital Design Engineer

Job Title

Digital Design Engineer

Role Summary

Design and implement front-end digital ASIC IP for high-speed parallel interfaces (DDR and die-to-die) within a high-speed interfaces team. Collaborate with architecture, verification, timing, and physical design engineers to deliver control and data-path blocks, low-power implementations, and silicon bring-up.

Experience Level

Mid-level - the posting specifies a minimum of 4+ years of ASIC design or related experience for this role; other degree/experience combinations are also described in the Education Requirements section.

Responsibilities

Primary responsibilities include:

• Design, develop and review RTL (SystemVerilog) for digital IP used in SoC-to-DRAM and multi-die links.
• Implement control and data-path blocks and drive front-end implementation flows.
• Perform logic synthesis, lint checks, and gate-level simulation bring-up and debug.
• Analyze and apply clock-domain crossing best practices.
• Implement low-power techniques and lead low-power sign-off activities.
• Support design-for-test (DFT) flows, including stuck and TDF modes.
• Collaborate with systems architecture, verification, timing, and physical design teams across implementation and silicon bring-up phases.
• Participate in integration, validation, and post-silicon debug activities.

Requirements

Must-have technical skills and experience:

• Minimum 4 years of ASIC digital design, verification, or related work experience.
• Proven RTL development experience using SystemVerilog.
• Experience with logic synthesis, linting, and gate-level simulation/debug.
• Clock-domain crossing (CDC) analysis and mitigation experience.
• Low-power implementation methodology and sign-off experience.
• Familiarity with DFT flows (stuck and TDF modes).
• Hands-on experience with ASIC front-end implementation tool flows and silicon bring-up.
• Ability to work effectively with cross-functional teams in a fast-paced environment.

Nice-to-have:

• Prior work on high-speed parallel physical interfaces (DDR, HBM, die-to-die).
• Experience in high-speed, low-power interfaces for compute/server applications.

Education Requirements

Posting indicates degree-based alternatives: a Bachelor's degree in Science, Engineering, or a related field is required for this role (posting also lists combinations such as Bachelor's +2 years, Master's +1 year, or PhD). Preferred examples include BS with 4 years' experience or MS with 2 years. Fields cited: Science, Engineering, or related technical fields.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.