Digital Architect

Job Title

Digital Architect

Role Summary

Own the top-level architecture for Snowcap's superconducting PCL digital chips, defining system partitioning, clocking, interconnect hierarchy, I/O boundaries, and the architectural test strategy. Translate device physics constraints into architectural requirements and deliver a definitive specification that downstream RTL, verification, physical design, and test teams use.

This is a hands-on, on-site role based in the San Francisco Bay Area or Jacksonville Metro; you will work closely with physics, microarchitecture, verification, physical design, and test in a flat startup environment.

Experience Level

Senior — lead/principal-level architect. The posting expects prior lead/principal architecture experience; no explicit years-of-experience were specified.

Responsibilities

Deliver and own the architecture specification and ensure it is defensible, buildable, and testable.

• Define system partitioning, block hierarchy, and the architecture document used by downstream teams.
• Develop clocking strategy for a non-CMOS logic family and design on-chip interconnect and I/O hierarchy, including cryogenic-to-room-temperature boundary considerations.
• Establish the chip-level test strategy and test protocol: specify observability, controllability, and what is verified where.
• Partner with physics leads to translate Josephson junction and PCL device behavior into architectural constraints and budgets; push back when necessary.
• Drive the architecture-to-microarchitecture handoff: produce the spec, defend it, and revise it based on downstream findings.
• Make compute/memory/interconnect tradeoffs with AI inference and HPC-class workloads as primary lenses.
• Set standards for clarity and rigor in Snowcap architecture documentation.

Requirements

Must-have qualifications and demonstrable experience required for this role.

• Lead or principal architect on a production digital chip program (CPU, GPU, TPU, NPU, or similar) with shipped silicon used for real workloads.
• Ability to reason from first-principles device physics constraints up to system-level architecture.
• Proven record of writing architecture specifications with documented rationale and tradeoffs.
• Deep, working understanding of clocking, interconnect, and I/O architecture at modern compute scale.
• Experience defining architectural-level test strategy and directing DFT decisions.
• Comfort operating with significant ambiguity in early-stage design within a startup environment.

Nice-to-have:

• Architecture work on AI inference accelerators (TPU/NPU/dataflow/tile-based machines) or HPC-class designs.
• Experience with non-standard logic families, asynchronous design, or wave-pipelined systems.
• Familiarity with superconducting digital logic families (PCL, SFQ, AQFP, RSFQ).
• Published architecture work, patents, or visible shipped products demonstrating architectural rationale.
• Cross-disciplinary fluency across circuits, devices, software, and workload analysis; mentorship or technical leadership of downstream teams.

Education Requirements

Not specified.

About the Company

Company: Snowcap Compute

Headquarters: San Francisco, CA, United States

Snowcap Compute develops commercial superconducting digital computers using Josephson junction–based PCL logic that operate at cryogenic temperatures, aiming for dramatically lower power than CMOS. The company combines expertise in quantum physics, cryogenic engineering, and semiconductor manufacturing to build production superconducting chips.