DFT Staff Engineer (Testchip Architecture)

Role Summary

The DFT Staff Engineer will lead the DFT architecture and methodology development for complex test-chip designs. This role involves defining and implementing various testing methodologies while ensuring integration and validation with design, verification, and physical design teams.

Experience Level

Mid-level, requiring a minimum of 7 years of experience in relevant fields.

Responsibilities

The engineer will be responsible for:

• Leading the DFT architecture for test-chip designs.
• Developing and maintaining DFT methodologies.
• Implementing Scan, Memory BIST, and ATPG standards.
• Providing post-silicon support.
• Collaborating with various teams to ensure seamless integration and validation.

Requirements

Must-have qualifications include:

• BSEE/MSEE or PhD in Electrical Engineering.
• 7+ years of hands-on experience with JTAG, Memory BIST, and ATPG.
• Proficiency in SystemVerilog and UVM-based verification environments.
• Expertise with ATPG and MBIST tools, particularly Tessent.
• Skills in testbench development, simulation, and debug.
• Experience in post-silicon failure analysis.
• Proficiency in scripting with Tcl, Python, and Shell.
• Experience in RTL development and functional verification is a plus.

Education Requirements

BSEE/MSEE or PhD in Electrical Engineering is required.

About the Company

Company: GlobalFoundries

Headquarters: Saratoga Springs, New York, USA

GlobalFoundries is a leading contract manufacturer for the global semiconductor industry, with facilities in multiple countries, including the USA. The company develops a broad portfolio of semiconductor technologies and employs around 13,000 people worldwide. GlobalFoundries focuses on enhancing competitiveness in specialized application solutions and fostering innovation in mobile communications, consumer electronics, and automotive applications.