DFT Staff Engineer

Job Title

DFT Staff Engineer

Role Summary

Lead design-for-test (DFT) implementation, verification, and debug for ASIC/SoC IP and chip projects within the ASICS Engineering team. Deliver robust scan/ATPG flows, coverage analysis, timing fixes, and test vector validation while collaborating with RTL designers, verification, and CAD teams.

Experience Level

Senior (Staff) level - the role expects an experienced DFT engineer. The posting indicates 8+ years of ASIC/DFT experience.

Responsibilities

Primary responsibilities include owning DFT deliverables for complex designs, developing and executing test flows, and supporting tapeout readiness.

• Define and implement DFT architecture and scan insertion flows for blocks and SoCs.
• Develop and run ATPG and coverage analysis; assess transition-delay test coverage.
• Define test-mode timing constraints and provide corrective actions for timing violations.
• Create and maintain automation scripts for DFT flows (Perl, shell, or similar).
• Simulate and validate test vectors and debug failing tests.
• Perform RTL lint/DFT DRC checks and support equivalence checks between RTL and gate-level where needed.
• Collaborate with cross-functional teams (design, verification, CAD) to integrate DFT into project schedules.
• Manage multiple high-priority designs in parallel and communicate results to stakeholders.

Requirements

Must-have technical skills and experience; a short list of preferred additions follows.

Must-have:

• 8+ years of hands-on ASIC/DFT experience with demonstrable DFT ownership on projects.
• In-depth knowledge of DFT concepts, scan insertion, ATPG, and coverage analysis.
• Experience with transition-delay test coverage analysis and test-mode timing constraint definition.
• Strong scripting skills (Perl, shell, or equivalent) to automate flows and analyses.
• Experience simulating and validating test vectors and debugging test failures.
• Familiarity with RTL lint DFT rules and ATPG tool flows (conceptual knowledge of DFT DRC and equivalence checks).
• Good problem-solving, communication, and teamwork skills; ability to work in international teams and handle multiple designs.

Nice-to-have:

• Hands-on experience with Synopsys TetraMax/DFTMax and Cadence Encounter Test.

Education Requirements

Bachelor's degree in Science, Engineering, or a related field with 4+ years of ASIC design/verification/DFT experience; OR Master's degree in Science, Engineering, or a related field with 3+ years of ASIC design/verification/DFT experience; OR PhD in Science, Engineering, or a related field with 2+ years of ASIC design/verification/DFT experience.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.