DFT Lead (Scan/ATPG) Engineer

Job Title

DFT Lead (Scan/ATPG) Engineer

Role Summary

Join the ACE India P-Core design team to lead design-for-test (DFT) activities for Intel CPUs in advanced process technology. The role focuses on scan/ATPG implementation, verification, and integration across RTL and production bring-up.

This position works with RTL designers, verification teams, EDA tools, and manufacturing/post-silicon teams to deliver robust testability and test patterns for processor cores.

Experience Level

Senior — typically requires 7+ years of relevant DFT experience (see Education Requirements for degree-related experience guidance).

Responsibilities

Primary responsibilities include leading DFT implementation and verification for P-Core features and supporting test bring-up.

• Lead DFT implementation for scan architectures, MBIST, TAP/IJTAG and related test features.
• Develop and integrate DFT logic into RTL; drive synthesis, timing, DRC, and ATPG flows.
• Create and debug ATPG patterns, fault grading, and coverage analysis across fault models.
• Use and mentor teams on EDA vendor tools (e.g., Tessent/TestKompress or similar) and ATPG shells.
• Coordinate with manufacturing and pattern delivery teams; support post-silicon and ATE bring-up.
• Collaborate with design verification teams using standard simulators and waveform tools.
• Mentor and provide technical leadership to junior engineers on DFT practices and tool flows.

Requirements

Technical skills and experience required for successful performance in this role.

• Strong knowledge of ATPG, fault models, and fault grading methodologies.
• Experience with memory BIST and IJTAG/TAP architecture and integration.
• DFT logic generation, integration, and verification in RTL flows.
• Experience with EDA-supported scan architectures and tool flows covering synthesis, timing analysis, ATPG, and GLS.
• Hands-on experience with tools such as Mentor/Siemens Tessent, TestKompress, or equivalent for ATPG and coverage debug.
• Experience with design verification using simulators and waveform viewers (e.g., VCS, Verdi).
• Post-silicon/ATE bring-up and tester bring-up experience.
• Proficiency with RTL languages: Verilog, SystemVerilog, and/or VHDL.
• Nice-to-have: prior collaboration with manufacturing engineering and pattern delivery teams.

Education Requirements

Master's degree in Electronics or Computer Engineering with at least 7 years of DFT experience, or a Bachelor's degree with at least 9 years of DFT experience (as stated by the employer).

About the Company

Company: Intel Corporation

Headquarters: Santa Clara, California, USA

Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.