DFT Lead Engineer
BitsilicaJob Title
DFT Lead Engineer
Role Summary
Lead DFT architecture and implementation for complex SoC and core designs. Work with RTL, verification, STA and ATPG teams to define and deliver scan insertion, compression, pattern generation, coverage and BIST solutions to meet testability and manufacturability goals.
Experience Level
Senior - 8 to 10+ years of DFT experience.
Responsibilities
Primary responsibilities include defining DFT strategy, implementing DFT features, and ensuring test coverage and manufacturability for cores and SoCs.
- Define and lead DFT architecture for core and SoC; drive scan insertion and compression strategies.
- Generate ATPG patterns and perform coverage analysis to meet test goals.
- Perform timing and no-timing simulations related to DFT and test flows.
- Design and validate Memory-BIST solutions and integration with SoC test flow.
- Incorporate SSN, clock architecture, and OCC considerations into DFT implementations.
- Collaborate with RTL design, verification, physical design and STA to integrate DFT solutions.
- Debug test failures, perform root-cause analysis, and refine test flows and patterns.
- Mentor and review deliverables from junior DFT engineers.
Requirements
Must-have technical skills and experience.
- 8 to 10+ years of hands-on experience in DFT architecture, scan insertion and compression at core and SoC levels.
- Experience in ATPG pattern generation and coverage analysis.
- Experience with timing and no-timing simulation flows related to DFT.
- Experience with Memory-BIST design and validation.
- Understanding of SSN architecture, clock architecture and OCC.
- Ability to collaborate across RTL, verification, STA and bring-ups; strong debugging and communication skills.
- Nice-to-have: familiarity with commercial ATPG tools and scripting for automation.
Education Requirements
Not specified.
About the Company
Company: Bitsilica
Headquarters: Mumbai, Maharashtra, India
Bitsilica is a technology company specializing in semiconductor design services, offering expertise in DFT (design for testability), ATPG, scan insertion, memory BIST, and SoC-level verification and architecture support.
