DFT Engineer - Verification

Job Title

DFT Engineer - Verification

Role Summary

Responsible for verifying ASIC DFT logic by building coverage-driven verification environments, executing verification plans, and collaborating with DFT design and manufacturing engineers to deliver reliable silicon.

Position is part of a small engineering team at a stealth-mode startup focused on scalable, resilient AI data center infrastructure; remote collaboration across U.S. and Canada.

Experience Level

Mid-level: 5+ years in digital design verification, with at least 2 years focused on DFT verification.

Responsibilities

Execute verification activities from planning to closure and improve verification infrastructure.

• Develop and maintain RTL verification environments using UVM or equivalent methodologies.
• Create and execute coverage-driven verification plans aligned with specifications.
• Use DFT EDA tools (e.g., TestMax, Tessent) to create and run pre-silicon test cases for MBIST and scan fabrics.
• Develop directed tests for non-vendor DFT logic and validate corner cases.
• Assist in verifying ATPG patterns and manufacturing reset sequences at SOC level.
• Analyze simulation results, debug complex issues, and perform root-cause analysis with design engineers.
• Implement and track functional and code coverage; drive verification to closure.
• Develop reusable verification components and write SystemVerilog Assertions (SVA).
• Automate regressions and enhance verification infrastructure using Python and scripting.
• Support post-silicon test bring-up and debug alongside DFT designers.

Requirements

Must-have technical skills and experience.

• 5+ years of digital design verification experience, with at least 2 years in DFT verification.
• Strong hands-on experience with UVM-based or similar verification methodologies.
• Proficiency in SystemVerilog and experience writing SVA.
• Experience with EDA simulators such as Synopsys VCS, Siemens/Mentor Questa, or Cadence Xcelium.
• Experience with DFT EDA tools such as Synopsys TestMax/Yield Accelerator or Siemens Tessent.
• Gate-level simulation experience and familiarity with tester pattern formats (e.g., STIL).
• Experience verifying test sequences for high-speed PHY logic (PCIe, Ethernet 10G/40G/100G).
• Proficiency in Python or similar scripting for automation and regression.
• Strong analytical, debugging, and written/verbal communication skills.

Nice-to-have:

• Experience with git and change-control systems.
• SoC-level verification experience.

Education Requirements

Bachelor's or Master’s degree in Electrical Engineering, Computer Engineering, or a related technical field.

About the Company

Company: Delos Data

Headquarters: Palo Alto, CA, United States

Stealth-mode Silicon Valley startup building foundational technology to improve performance, scalability, and resiliency of large-scale AI data center clusters. Backed by venture capital and led by experienced founders, the company develops hardware/software solutions and operates across U.S. and Canadian locations.