DFT Engineer, Senior

Job Title

DFT Engineer, Senior

Role Summary

As a Senior DFT (Design-for-Test) engineer you will define and execute DFT architecture, implement RTL-based test structures, verify test insertion and patterns pre-silicon, and support silicon bring-up and yield improvement. You will work within the hardware engineering team and collaborate with physical design, test, and validation teams to ensure manufacturable designs with high test coverage.

Experience Level

Senior. See Education Requirements for degree and specific experience equivalencies.

Responsibilities

Primary responsibilities include DFT architecture, pre-silicon verification, silicon bring-up, and automation.

• Define and execute end-to-end DFT strategy (scan, boundary-scan/JTAG, memory and logic BIST).
• Insert DFT structures into RTL and verify insertion flows.
• Generate and validate ATPG test patterns (Stuck‑At, at‑speed, path‑delay); apply scan compression and data‑streaming techniques to reduce test time.
• Design and implement MBIST and LBIST architectures in RTL and validate them.
• Perform gate-level timing and power-aware simulations to validate DFT implementations.
• Partner with physical design and test engineering teams to resolve timing/DFT issues and drive yield improvements during silicon bring-up.
• Diagnose failing patterns and collaborate on root-cause analysis and yield fixes.
• Develop and maintain automation scripts and flows (Python, Tcl, Perl).

Requirements

Required technical skills and practical experience for successful performance in this role.

• Hands-on experience with DFT insertion and verification flows and standard ATPG tools.
• Experience implementing and validating MBIST/LBIST architectures in RTL.
• Practical use of scan compression and other test-time reduction techniques.
• Gate-level simulation and timing/power-aware verification experience.
• Experience in silicon bring-up, test failure diagnosis, and driving yield improvements.
• Proficient scripting for automation (Python, Tcl, or Perl).
• Strong collaboration skills with physical design, test, and validation teams.
• Experience deploying agentic AI tools to optimize semiconductor workflows.

Nice-to-have: prior work on complex SoC DFT for high-performance processors or memory subsystems.

Education Requirements

Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field plus 2+ years of hardware engineering or related experience; OR Master's degree in those fields plus 1+ year of relevant experience; OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field. The posting allows the listed degree options with the specified experience equivalencies.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.