DFT Engineer, High-Performance Chip Focus

Job Title

DFT Engineer, High-Performance Chip Focus

Role Summary

Work on end-to-end Design-for-Test (DFT) flow for high-performance ASICs. The role supports digital design and test teams to ensure chips are testable and debug-ready at production.

Primary focus is on implementing and maintaining DFT infrastructure, automation, and testability for complex digital designs.

Experience Level

Mid-level — typically 3–5 years of experience in DFT or digital design.

Responsibilities

Key responsibilities include delivering and supporting DFT solutions across the chip design cycle.

• Design, implement, and maintain DFT structures and flows (scan, BIST, test insertion).
• Develop scripts and automation for DFT flows using Tcl, Python, or similar languages.
• Collaborate with digital design, verification, and validation teams to ensure testability and debug readiness.
• Generate and validate test patterns; assist with silicon debug and bring-up activities.
• Document DFT procedures and provide ongoing support to design teams.

Requirements

Must-have technical skills and experience.

• 3–5 years of practical experience in DFT or digital design.
• Strong understanding of digital logic and testability concepts.
• Proficiency in scripting for automation (Tcl and Python preferred).
• Experience integrating DFT into ASIC flows and working with multi-team design processes.
• Good debugging, problem-solving, and communication skills.
• Nice-to-have: experience with high-performance chips, at-speed testing, or familiarity with common DFT/EDA toolchains.

Education Requirements

Posting references "a relevant degree." Expected: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field. The posting does not specify exact degree levels or mention explicit alternative-equivalent experience language.

About the Company

Company: Beacon Industries

Technology/engineering company focused on analog and mixed-signal integrated circuit design and custom IC layout (SerDes, SRAM, high-speed interfaces), using Synopsys/Cadence EDA tools for design, simulation, verification, and silicon validation.