DFT Engineer (Design for Test)

Job Title

DFT Engineer (Design for Test)

Role Summary

The DFT Engineer will design and implement design-for-test solutions for ASIC and SoC projects, ensuring manufacturability, test coverage, and efficient production testing. The role works within a cross-functional ASIC/SoC engineering team and supports silicon bring-up through production test.

Experience Level

Mid-level — 5+ years of hands-on DFT experience.

Responsibilities

Key responsibilities include:

• Design and implement DFT architecture for ASIC and SoC designs.
• Develop and integrate Scan Compression, MBIST, LBIST, JTAG, and IJTAG solutions.
• Perform ATPG, fault simulation, and test coverage analysis.
• Support silicon bring-up, debug, characterization, and production test activities.
• Collaborate with Design, Verification, Physical Design, and Product Engineering teams.

Requirements

Must-have technical skills and experience:

• 5+ years of hands-on Design for Test (DFT) experience.
• Strong expertise in Scan, Scan Compression, MBIST, LBIST, ATPG, and JTAG.
• Knowledge of IEEE 1149.1, IEEE 1500, and IEEE 1687 (IJTAG) standards.
• Experience with industry DFT tools such as Synopsys TestMAX/DFT Compiler, Siemens Tessent, or Cadence Modus.
• Proficiency in Verilog and/or SystemVerilog.
• Scripting skills in Python, Perl, Tcl, or Shell.

Nice-to-have:

• Experience with ASIC/SoC development lifecycle.
• Background in silicon bring-up, debug, and production test.
• Strong cross-functional problem-solving and communication skills.

Education Requirements

Not specified.

About the Company

Company: CaritaTech

Engineering staffing and consulting firm providing placement and contract services for hardware, semiconductor, and embedded systems professionals, including roles in SoC/ASIC physical design and verification.