DFT Engineer (Design for Test)

Job Title

DFT Engineer (Design for Test)

Role Summary

Design and implement Design-for-Test (DFT) solutions for ASIC/SoC projects to ensure manufacturability, high test coverage, and efficient production testing. The role sits on an ASIC/SoC engineering team and works across design, verification, physical design, and product engineering.

Experience Level

Mid-level — requires 5+ years of hands-on DFT experience.

Responsibilities

Key responsibilities include:

• Define and implement DFT architecture for ASIC and SoC designs.
• Develop and integrate Scan Compression, MBIST, LBIST, JTAG, and IJTAG solutions.
• Perform ATPG, fault simulation, and test coverage analysis.
• Support silicon bring-up, debug, characterization, and production test activities.
• Collaborate with Design, Verification, Physical Design, and Product Engineering during the development lifecycle.

Requirements

Must-have and preferred qualifications:

• Must-have: 5+ years of hands-on Design-for-Test (DFT) experience.
• Must-have: Strong expertise in Scan, Scan Compression, MBIST, LBIST, ATPG, and JTAG technologies.
• Must-have: Solid understanding of IEEE 1149.1, IEEE 1500, and IEEE 1687 (IJTAG) standards.
• Must-have: Experience with one or more industry DFT tools such as Synopsys TestMAX / DFT Compiler, Siemens Tessent, or Cadence Modus.
• Must-have: Proficiency in Verilog and/or SystemVerilog.
• Must-have: Scripting experience (Python, Perl, Tcl, or Shell).
• Preferred: Experience with ASIC/SoC development and production test.
• Preferred: Background in silicon bring-up and debug.
• Preferred: Strong problem-solving skills and ability to work effectively in cross-functional teams.

Education Requirements

Not specified.

About the Company

Company: CaritaTech

Engineering staffing and consulting firm providing placement and contract services for hardware, semiconductor, and embedded systems professionals, including roles in SoC/ASIC physical design and verification.