DFT Engineer
Select MindsJob Title
DFT Engineer
Role Summary
Join an ASIC/SoC engineering team to design and implement Design-for-Test (DFT) solutions that improve manufacturing yield, test coverage, and production test efficiency for complex semiconductor devices.
This role works onsite with cross-functional teams through design, verification, silicon bring-up, and production test phases.
Experience Level
Mid-level — 5+ years of hands-on DFT experience preferred.
Responsibilities
The engineer will develop, integrate, and validate DFT features and support silicon test activities.
- Design and implement DFT architecture for ASIC and SoC designs.
- Develop and integrate Scan Compression, MBIST, LBIST, JTAG, and IJTAG solutions.
- Perform ATPG, fault simulation, and test coverage analysis.
- Support silicon bring-up, debug, characterization, and production test.
- Collaborate with Design, Verification, Physical Design, and Product Engineering teams.
Requirements
Must-have technical skills and experience for immediate contribution.
- 5+ years of hands-on Design-for-Test (DFT) experience.
- Strong expertise in Scan, Scan Compression, MBIST, LBIST, ATPG, and JTAG technologies.
- Familiarity with IEEE 1149.1, IEEE 1500, and IEEE 1687 (IJTAG) standards.
- Experience with industry DFT tools such as Synopsys TestMAX/DFT Compiler, Siemens Tessent, or Cadence Modus.
- Proficiency in Verilog and/or SystemVerilog.
- Scripting experience with Python, Perl, Tcl, or shell scripting.
Nice-to-have:
- Experience with ASIC/SoC development and production test flows.
- Background in silicon bring-up, debug, and production test engineering.
- Strong problem-solving skills and cross-functional teamwork experience.
Education Requirements
Not specified.
About the Company
Company: Select Minds
Select Minds is a staffing and recruitment firm that sources engineering and technical talent for technology employers, handling contract and direct-hire placements in areas such as semiconductor and ASIC design.
