DFT Engineer

Job Title

DFT Engineer

Role Summary

Design-for-Test (DFT) engineer responsible for defining DFT requirements and implementing DFT solutions for IP/blocks and SoC level alongside backend and test teams. The role focuses on scan insertion, ATPG pattern generation and verification, MBIST and memory repair, silicon bring-up support, and improving test coverage and test time.

Experience Level

Senior — requires 7+ years of DFT execution experience on mixed-signal SoCs with first-pass silicon success.

Responsibilities

Key responsibilities include specification, insertion, verification and support activities across RTL-to-silicon DFT flows:

• Define and document DFT requirements/specifications for IP, block and chip levels.
• Perform DFT lint to find and resolve scan DRC violations.
• Insert scan at top-level and hard-macro block level with high EDT compression (Hybrid LBIST, EDT IP/ATPG, LPCT EDT) and AC/at-speed scan verification.
• Plan and insert MBIST and BISR for memories at RTL; generate and port IJTAG ICL/PDL and STIL patterns for MBIST, ATPG and JTAG tests.
• Verify ATPG patterns on pre- and post-route gate-level netlists, both 0-delay and SDF back-annotated simulations.
• Coordinate with backend for MBIST/scan-mode constraints, scan reordering, VCDs for IR-drop analysis, ECO changes, formal LEC checks and timing closure.
• Support test engineering: pattern generation, tester debug, failure analysis, silicon bring-up and ATE validation for development and production.
• Maintain and extend flows and scripts required for debugging, diagnosing and production test programs.

Requirements

Must-have skills and experience; select nice-to-have items listed separately.

• Must-have: 7+ years hands-on hierarchical DFT flow experience from RTL to netlist on mixed-signal SoC with first-pass silicon success.
• Strong experience with JTAG (IEEE 1149.1) and IJTAG (IEEE 1687) and generating IJTAG ICL/PDL/STIL patterns.
• Proven expertise in ATPG, including pattern generation, fault coverage analysis, and resolving ATPG DRC and chain trace issues.
• Experience inserting EDT, wrapper cells and OCC, and planning/implementing MBIST and memory repair (BISR).
• Gate-level simulation and debug experience (0-delay and SDF); familiarity with VCDs for IR-drop and ECO impact analysis.
• Proficient with Mentor Tessent toolchain and experience using Cadence for scan stitching.
• Experience debugging tester/ATE failures, silicon bring-up, yield and test-time improvement.
• Practical scripting skills (Perl/TCL) and effective verbal/written communication.

Education Requirements

Not specified.

About the Company

Company: Retym Israel

Technology company hiring VLSI/ASIC digital design engineers for communication systems and SoC/IP development. Work includes RTL design, verification, synthesis, timing closure, and silicon bring-up.