DFT Engineer

Job Title

DFT Engineer

Role Summary

Senior DFT verification engineer responsible for validating ASIC DFT logic and delivering reliable silicon. Work with DFT design and manufacturing engineers to build verification environments, execute coverage-driven plans, and close verification across RTL, gate-level, and SOC integration.

Experience Level

Senior - typically 5+ years in digital verification, with at least 2 years focused on DFT verification.

Responsibilities

Primary responsibilities include building verification infrastructure, executing targeted and coverage-driven tests, and supporting post-silicon bring-up.

• Develop and maintain RTL verification environments using UVM or equivalent methodologies.
• Create and execute coverage-driven verification plans aligned with design specs.
• Use EDA DFT tools (e.g., TestMax, Tessent) to generate and run MBIST and scan fabric tests inserted by those tools.
• Develop directed tests for non-vendor DFT logic and validate corner cases.
• Verify ATPG patterns at SOC level and validate manufacturing reset sequences.
• Analyze simulation results, debug complex verification and design issues, and perform root-cause analysis with design engineers.
• Implement and track functional and code coverage and drive verification to closure.
• Develop reusable verification components and write SystemVerilog Assertions (SVA).
• Automate regression testing and enhance verification infrastructure using Python and scripting.
• Support post-silicon test bring-up debug alongside DFT designers.

Requirements

Must-have technical skills and experience; preferred items listed separately.

• 5+ years in digital design verification, with at least 2 years in DFT verification specifically.
• Strong hands-on experience with UVM-based or similar verification methodologies.
• Proficiency in SystemVerilog.
• Experience with industry-standard simulators (e.g., Synopsys VCS, Siemens/Mentor Questa, Cadence Xcelium).
• Experience with EDA DFT tools (e.g., Synopsys TestMax/Yield Accelerator, Siemens Tessent) for MBIST and scan testing.
• Experience with gate-level simulation and tester pattern formats such as STIL.
• Experience verifying test sequences for high-speed PHY logic (PCIe, Ethernet 10G/40G/100G).
• Proficiency in scripting and automation, preferably Python.
• Strong analytical, debugging, and cross-functional communication skills.
• Ability to work independently and manage tasks to completion.
• Nice-to-have: experience with git/change control systems; experience verifying SoC-level designs.

Education Requirements

Bachelor's or Master’s degree in Electrical Engineering, Computer Engineering, or a related field; or equivalent practical experience.

About the Company

Company: Delos Data

Headquarters: Palo Alto, CA, United States

Stealth-mode Silicon Valley startup building foundational technology to improve performance, scalability, and resiliency of large-scale AI data center clusters. Backed by venture capital and led by experienced founders, the company develops hardware/software solutions and operates across U.S. and Canadian locations.