Job Title
DFT Engineer
Role Summary
Design and implement testability features for SoC/ASIC projects, focusing on scan, ATPG, MBIST, IO test, and clock DFT. Work within a semiconductor design program to enable manufacturing test, fault diagnosis, and delivery of robust test solutions.
Experience Level
Mid-level (5+ years of hands-on DFT/ATPG experience)
Responsibilities
Deliver and validate design-for-test features across digital ASIC/SoC projects. Typical responsibilities include:
- Develop and implement scan architectures and DFT strategies to meet testability and coverage goals.
- Create and analyze ATPG patterns; debug test failures and pattern generation issues.
- Design and validate MBIST solutions and memory diagnostics.
- Define and execute IO and pin-level test methodologies.
- Implement and verify clock DFT and clock-domain test strategies.
- Collaborate with RTL, verification, and physical design teams to integrate DFT features.
- Use industry-standard DFT/ATPG EDA tools to produce deliverables and reports.
- Document test plans, debug sessions, and provide diagnostics for production bring-up.
Requirements
Must-have technical skills and attributes:
- 5+ years of hands-on DFT and ATPG experience for SoC or ASIC designs.
- Strong understanding of DFT fundamentals: controllability, observability, and scan-based testing.
- Proven expertise in ATPG pattern generation, analysis, and debug.
- Experience with MBIST, memory test architectures, and diagnostics.
- Knowledge of IO test methodologies and pin-level validation.
- Solid understanding of clock DFT and clock verification concepts.
- Good grasp of digital design and RTL fundamentals.
- Experience with industry-standard DFT/ATPG EDA tools.
- Ability to work effectively in fast-paced semiconductor programs; strong analytical and communication skills.
Education Requirements
BE (Bachelor of Engineering) degree reported. No additional degree fields or equivalent-experience language specified.
About the Company
Company: ForwardEdge ASIC
Engineering company focused on ASIC and FPGA design and verification, providing verification strategy, testbench development, and technical leadership for complex high-performance chip designs. Supports projects requiring US government security clearances.

Date Posted: 2026-06-01