DFT Engineer

Job Title

DFT Engineer

Role Summary

Work on design-for-test (DFT) implementation and ATPG for SoC/ASIC projects at an engineering program level. The role focuses on creating and validating test structures, generating and analyzing ATPG patterns, and ensuring memory and IO testability.

Collaborate with digital/RTL designers and verification teams to integrate DFT, MBIST, IO test, and clock-domain test solutions, and support diagnostics and test debug on silicon.

Experience Level

Mid-level — requires 5+ years of hands-on DFT and ATPG experience for SoC or ASIC designs (typical mid-career range 3–7 years).

Responsibilities

Primary responsibilities include DFT implementation, ATPG generation and debug, and memory and IO test preparation.

• Develop and implement scan-based DFT strategies to meet testability goals.
• Generate, analyze, and debug ATPG patterns; assess test coverage and fault diagnostics.
• Design and validate MBIST and memory test architectures and diagnostics.
• Define and verify IO test methodologies and pin-level validation.
• Address clock DFT issues and perform clock verification related to testability.
• Collaborate with RTL and verification teams to ensure DFT integration and resolve testability issues.
• Use industry-standard DFT/ATPG EDA tools for implementation and analysis.
• Provide technical problem solving, debug support, and clear communication to program stakeholders.

Requirements

Must-have technical skills and experience for immediate contribution.

• 5+ years of hands-on experience in DFT and ATPG for SoC or ASIC designs.
• Strong understanding of controllability, observability, and scan-based testing.
• Proven expertise in ATPG pattern generation, analysis, and debug.
• Experience with MBIST architectures and memory diagnostics.
• Knowledge of IO test methodologies for interface and pin validation.
• Solid understanding of clock DFT and clock verification concepts.
• Strong grasp of digital design and RTL fundamentals.
• Experience with industry-standard DFT/ATPG EDA tools.
• Effective analytical, problem-solving, and communication skills; ability to work in fast-paced semiconductor programs.
• Nice-to-have: Not specified.

Education Requirements

Bachelor of Engineering (BE) required. Field of study not specified.

About the Company

Company: ForwardEdge ASIC

Engineering company focused on ASIC and FPGA design and verification, providing verification strategy, testbench development, and technical leadership for complex high-performance chip designs. Supports projects requiring US government security clearances.