DFT (Design For Test) Engineer

Job Title

DFT (Design For Test) Engineer

Role Summary

Senior DFT engineer responsible for designing and validating test architectures for ASIC and SoC products, from pre-silicon implementation through production. Work cross-functionally with design, verification, test, manufacturing, and quality teams to ensure high test coverage, yield, and reliable silicon bring-up.

Position is on-site in San Jose, contributing to product-quality, test strategy, and automated production test development for high-performance inference ASICs.

Experience Level

Senior — typically requires 10+ years of DFT experience in ASIC or SoC environments.

Responsibilities

Primary responsibilities include implementing and validating DFT solutions, supporting silicon bring-up, and enabling production testability.

• Design and implement DFT architectures (scan, boundary scan, BIST, MBIST) for ASIC/SoC designs.
• Integrate DFT requirements early with design and verification teams; participate in design reviews and DFT audits.
• Create and execute DFT verification plans using simulation and formal techniques to validate DFT logic.
• Analyze test results and silicon debug data to provide corrective design feedback and improve coverage and yield.
• Support post-silicon bring-up, failure analysis, and debug to ensure successful product launch.
• Collaborate with test engineering to develop and optimize ATE programs and generate production-quality test patterns.
• Document DFT architectures, test plans, procedures, and debug guides; share best practices and mentor team members.
• Monitor manufacturing and quality metrics and implement data-driven test process improvements.

Requirements

Must-have technical skills and experience; nice-to-have items listed separately.

• Extensive hands-on DFT experience (10+ years preferred) with successful implementations for ASIC or SoC products.
• Deep understanding of digital design and verification methodologies and DFT implementation practices.
• Proficiency in SystemVerilog and experience with industry-standard EDA DFT tools (examples: Synopsys DFT Compiler, Cadence Encounter Test, Mentor Tessent).
• Scripting and automation skills (Python, Perl, or TCL) to streamline DFT flows and test generation.
• Strong analytical and debugging skills for pre- and post-silicon failure analysis.
• Proven ability to lead DFT initiatives across product generations and collaborate cross-functionally.

Nice-to-have:

• Experience with mixed-signal DFT integration and analog testability for SoCs.
• Familiarity with industry standards such as IEEE 1149.1 (JTAG) and IEEE 1500.
• Experience in yield analysis, test cost reduction, and high-volume production test environments.

Education Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field is required; Master’s degree preferred. (No alternative "equivalent experience" language specified.)

About the Company

Company: Etched

Headquarters: San Jose, CA, United States

Etched develops purpose-built AI inference ASICs and systems optimized for transformer models, aiming to deliver significantly higher performance, lower cost, and lower latency than GPUs. The company focuses on enabling applications like real-time video generation and advanced reasoning agents, and is backed by leading investors and engineers.