DFT Design Engineer

Role Summary

Central DFX (CDFX) is a centralized ASIC design group within AMD’s Technology and Engineering organization. CDFX has a global footprint with design teams located in several AMD offices in North America and Asia. Our mandate is to optimize and standardize design methodology, design and implementation of critical Design-for-Test (DFT) and Design-for-Debug (DFD) features for complex state-of-the-art APU computing, game console and GPU graphics products. It is also responsible for DFX design methodology and CAD automation tools development to support the global DFX engineering teams across AMD.

Experience Level

Level - Mid-Career

Responsibilities

• Understand Design-for-Test (DFT) and Design-for-Debug (DFD) architecture.
• Implement and deploy automated design flows to implement DFT features in a complex SOC ASIC design or IP subsystem.
• Perform scan ATPG design rule checking, pattern generation, simulation and coverage analysis.
• Collaborate with IP teams to configure and embed DFT RTL.
• Setup and execute design checks using both industry standard and in-house tools.
• Deliver Perl, TCL scripts that provide scalable solutions key to DFT implementation.
• Create block-/chip-level Design Verification (DV) test plan.
• Develop test cases, behavioral functional models and testbench.
• Verify block-/chip-level DFT/DFD features.
• Monitor CAD and/or IP regression results, debug failures and analyze coverage.

Requirements

• Experience with Perl/Shell scripting and C.
• Digital circuits and VLSI knowledge.
• Experience with Verilog environment is an asset.
• Strong problem-solving skills.
• Good object-oriented programming skills (C++) is a must.
• Good written and oral communication skills.
• Team player with strong interpersonal skills.
• Industry DFT experience.

Education Requirements

Bachelors or Masters degree in computer engineering/Electrical Engineering.