DFT ATPG Design and Test Engineer

Job Title

DFT ATPG Design and Test Engineer

Role Summary

Responsible for delivery of scan test patterns, ATPG analysis, and test bring-up to ensure manufacturing readiness and product quality for next-generation CPU cores and cache subsystems.

Member of the Cores Organization working with design, physical design, and product test teams; role is based in Fort Collins with a hybrid work model.

Experience Level

Mid-level. The posting does not specify a years-of-experience requirement.

Responsibilities

Primary responsibilities include:

• Generate, validate, and deliver scan test patterns for CPU cores and caches.
• Support product test bring-up and troubleshoot pattern, model, and netlist issues.
• Improve scan architecture, scan coverage, test models, and execution methods.
• Perform ATPG pattern and gate-level netlist analysis to identify and resolve testability and coverage issues.
• Collaborate with physical design for design closure via static timing, clock-domain crossing, netlist, and power analysis.
• Address DFT requirements for high-frequency CPU designs while minimizing performance impact.
• Resolve interactions between IP and SoC design environments across distributed teams.
• Develop and implement improvements that simplify design complexity and strengthen engineering quality.
• Contribute to the evolution of CPU cache array and DFT design practices.

Requirements

Critical skills and qualifications for successful candidates.

• Must-have: Practical experience with design-for-test methodologies, especially scan test and ATPG.
• Must-have: Experience debugging ATPG patterns, scan structures, test models, and gate-level netlists.
• Must-have: Working knowledge of industry-standard ATPG tools and their application to pattern generation and fault coverage.
• Must-have: Familiarity with multi-clock and multi-power-domain designs and basic static timing/CDC analysis.
• Must-have: Proven ability to collaborate across design, physical design, product engineering, and geographically distributed teams.
• Must-have: Authorization to work in the United States; this role is not eligible for visa sponsorship.
• Nice-to-have: Understanding of IEEE 1149.1 boundary scan, IEEE 1500 embedded core test, and memory BIST concepts.
• Nice-to-have: Experience adapting DFT methods for high-frequency CPU designs and familiarity with CPU/cache architecture.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related technical field is preferred.

About the Company

Company: Advanced Micro Devices

Headquarters: Sunnyvale, California, USA

Advanced Micro Devices, or AMD, is a global semiconductor company that designs and manufactures microprocessors, graphics processors, and related technologies for a variety of computing devices. Known for pushing the boundaries of innovation, AMD's mission is to deliver high-performance computing solutions for AI, data centers, gaming, and embedded applications. They foster a collaborative, inclusive culture focused on creativity and problem-solving, aiming to drive progress and excellence in technology.