DFT Architect / Lead

Job Title

DFT Architect / Lead

Role Summary

The DFT Architect / Lead defines and owns Design-for-Test (DFT) architecture and test strategy for complex, high-performance SoCs. The role drives end-to-end DFT approaches from RTL through silicon bring-up and HVM, working with cross-functional teams to minimize test cost and improve yield.

Experience Level

Level - Senior. The role requires 7+ years of hands-on DFT experience, including multiple SoC tape-outs and first-silicon bring-up.

Responsibilities

Lead DFT architecture, methodology, and silicon lifecycle activities across projects and teams.

• Define and own global DFT architecture: hierarchical scan, compressed ATPG, MBIST/LBIST, IEEE 1687 (IJTAG) networks, and multi-die/chiplet test schemes.
• Develop defect-oriented test strategies and optimize pattern volume versus tester memory and test time.
• Integrate DFT requirements into RTL, synthesis, STA/PD and physical design flows; drive DFM initiatives.
• Lead silicon bring-up, post-silicon validation, root-cause analysis, and ATE/system-level failure debug.
• Architect and maintain automated DFT flows using TCL, Python, or Perl; evaluate EDA tool capabilities for advanced process nodes.
• Mentor engineers and consult with RTL/DV/PD/STA teams to prevent timing or routing issues introduced by DFT structures.
• Author DFT specifications and strategy documents; at times lead device execution from spec through integration to silicon bring-up.
• Support Environmental, Health, Safety & Security requirements in all activities.

Requirements

Must-have technical skills and demonstrable experience.

• 7+ years of hands-on DFT experience with multiple complex SoC tape-outs and proven silicon debug experience (first-silicon bring-up, characterization, customer debug, production ramp).
• Expert-level proficiency with industry DFT/ATPG tool suites (examples: Synopsys TestMAX/DFTMAX, Cadence Modus, Siemens/Mentor Tessent).
• Deep knowledge of scan compression architectures, hierarchical DFT, and mixed-signal test integration.
• Advanced scripting skills in TCL and Python or Perl for CAD flow automation and custom attributes.
• Ability to resolve timing closure and ATPG coverage issues introduced by DFT structures.
• Strong written and verbal technical documentation skills to produce DFT specifications and strategies.

Nice-to-have:

• Experience with Automotive ASIL-D functional safety flows, In-System Test (IST), and periodic monitoring.
• Knowledge of 2.5D/3D IC testing, TSV probing, or HBM test strategies.
• Experience with volume diagnostics, yield learning, and DPPM reduction tools.
• Active participation in technical conferences or contributions to patented DFT innovations.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related technical field.

About the Company

Company: GlobalFoundries

Headquarters: Saratoga Springs, New York, USA

GlobalFoundries is a leading contract manufacturer for the global semiconductor industry, with facilities in multiple countries, including the USA. The company develops a broad portfolio of semiconductor technologies and employs around 13,000 people worldwide. GlobalFoundries focuses on enhancing competitiveness in specialized application solutions and fostering innovation in mobile communications, consumer electronics, and automotive applications.