DFT and Test Engineer

Job Title

DFT and Test Engineer

Role Summary

Responsible for ensuring testability is designed into hardware during the design phase at the Richardson, TX site. The role reviews schematics and layouts against DFT rules, models structural and functional coverage against MTRS, and supports early build debug and functional test definition.

Works cross-functionally with schematic/layout engineers, firmware/software teams, test operations, and the program TRL to close coverage gaps before layout freeze.

Experience Level

Mid-level - typically 4 to 8 years of experience in Design for Testability (DFT) or Test Engineering in complex electronics environments.

Responsibilities

Primary responsibilities include reviewing designs for testability and delivering coverage evidence and formal dispositions.

• Review schematics and layouts against DFT rules before layout freeze and document findings with supporting evidence.
• Model structural and functional test coverage against the MTRS and report coverage gaps.
• Verify achieved coverage on the first fixture and record differences from initial claims.
• Collaborate with schematic/layout engineers, software/firmware teams, site test engineering, and the DFT manager to disposition coverage gaps via test point additions, chain corrections, or agreed alternatives.
• Support functional test definition and early build debug alongside the Test Readiness Lead and on-site test SMEs.
• Propose DFT rule changes based on test escapes and fixture rework feedback to improve design standards.
• Own deliverables: testability reviews, coverage models, DFT findings with formal dispositions, achieved coverage evidence, and rule-change proposals; performance measured on first-fixture coverage, pre-freeze closed findings, and test escape rates.

Requirements

Must-have technical skills, tooling experience, and working conditions.

• Strong expertise in Design for Testability (DFT): test point access, boundary-scan chains, debug access, and provisioning access.
• Hands-on proficiency with Boundary Scan, In-Circuit Test (ICT), and coverage analysis tools.
• Experience modeling structural and functional coverage and reporting against coverage standards (e.g., MTRS).
• Proven collaborative problem-solving and strong cross-functional communication skills.
• Ability to document findings, produce formal dispositions, and maintain evidence of achieved coverage.
• Comfortable working in a normal office environment; may require extended sitting, sustained visual concentration, repetitive manual tasks, and occasional travel.
• Ability to work on-site at a US ITAR facility; successful hire will require providing information to determine export-control exemptions or licenses.

Education Requirements

Bachelor's degree in Electrical Engineering, Electronic Engineering, or a related technical discipline is typical.

About the Company

Company: Celestica

Headquarters: Toronto, Ontario, Canada

Global design, engineering, and manufacturing services company providing hardware, supply chain and platform solutions for data center, aerospace, defense, healthtech and advanced electronics customers. Offers engineering-led services across design, manufacturing, and lifecycle support with a global network.