Design Verification Staff Engineer

Job Title

Design Verification Staff Engineer

Role Summary

Staff-level verification engineer responsible for deploying and supporting constraint verification, RTL-quality, and simulation-based timing validation flows for strategic semiconductor accounts in Hsinchu. Work spans customer-facing methodology deployment, on-site debugging, automation, training, and feedback to R&D and product management.

Experience Level

Senior - typically 10+ years of hands-on experience in digital design implementation, static timing analysis, RTL verification, or signoff methodologies.

Responsibilities

Lead customer-facing technical engagements to deploy and operationalize verification and timing solutions.

• Lead full-cycle deployments of Timing Constraints Management (TCM), VC SpyGlass, and VCS from evaluation to production and methodology integration.
• Debug complex timing-constraint issues: false-path validation, multi-cycle paths, CDC verification, and STA-to-simulation correlation in real designs.
• Drive pilot projects to validate constraint verification, RTL quality checks, and simulation-based timing validation in advanced-node SoCs.
• Develop automation scripts and reusable deployment methodologies (Tcl, Python, Perl) to improve customer productivity and time-to-signoff.
• Deliver technical workshops and hands-on training for constraint management, lint/CDC/RDC flows, and simulation debug techniques.
• Collaborate with R&D to escalate customer issues, validate new features, and influence product roadmaps.
• Work with sales and product teams to identify expansion opportunities and translate customer pain points into technical solutions.

Requirements

Must-have technical skills and experience for immediate contribution; nice-to-have items noted.

• 10+ years of hands-on experience in digital implementation, static timing analysis, RTL verification, or signoff methodologies in production environments.
• Deep working knowledge of SDC constraints, timing exceptions, false-path and multi-cycle path analysis, clock-domain crossing, and timing closure flows.
• Proven experience debugging STA-to-simulation correlation and timing issues using tools such as PrimeTime or Tempus.
• Strong background in lint, CDC, RDC, and structural verification methodologies; experience with VC SpyGlass or equivalent.
• Proficiency scripting in Tcl, Python, Perl, or shell for automation and flow development.
• Experience building deployable methodologies and customer-facing automation that scale across teams.
• Nice-to-have: experience with advanced-node SoC/ASIC designs and enterprise-scale verification deployments.

Education Requirements

MS in Electrical Engineering, Computer Engineering, or an equivalent technical discipline is specified; equivalent practical experience is acceptable.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.