Design Verification Senior to Staff Engineer

Role Summary

The Design Verification Senior to Staff Engineer will be part of Marvell Central Engineering, developing advanced High-Speed SerDes (HSS) IPs across multiple applications. The role involves analyzing specifications, creating test plans, contributing to UVM component development, and improving coverage results.

Experience Level

Mid-level, typically requiring 2-7 years of related professional experience with a bachelor’s degree or 1-5 years with a Master’s degree or PhD.

Responsibilities

The responsibilities for this position include:

• Analyze specifications and create comprehensive test plans.
• Develop UVM components, coverage models, and assertion protocol checkers.
• Run simulations, regression, debug, and propose bug fixes.
• Improve coverage results through analysis.
• Run GLN/SDF simulations and propose ECO fixes.

Requirements

The ideal candidate will have the following:

• Bachelor’s degree in Computer Science, Electrical Engineering, or related fields, or a Master’s/PhD with relevant experience.
• Experience in Verilog and SystemVerilog, preferably with UVM.
• Proficiency in C and C++ programming.
• Knowledge of Digital Signal Processing (DSP) theory is a plus.
• Experience with scripting languages such as Python or Perl.
• Working knowledge of Linux.
• Proficiency in English.

Education Requirements

Bachelor’s degree in Computer Science, Electrical Engineering, or related fields; Master’s degree or PhD preferred.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.