Design Verification Senior Staff Engineer

Job Title

Design Verification Senior Staff Engineer

Role Summary

Lead end-to-end SoC design verification for data-center compute and storage ASICs within the Compute & Storage BU. Own verification strategy, test-plan definition, testbench architecture and sign-off across IP, subsystem and SoC levels.

Work cross-functionally with design, emulation, silicon bring-up and program teams to ensure correct functionality, coverage closure and successful post-silicon validation.

Experience Level

Senior — typically 8+ years of relevant verification experience.

Responsibilities

Accountable for verification planning, execution, and delivery for complex SoC projects.

• Lead SoC-level verification execution, milestone tracking and sign-off.
• Define and improve DV processes to increase efficiency and quality.
• Create test plans and architect/implement simulation testbenches (UVM & C).
• Collaborate with IP, subsystem and SoC design teams for test development, debug and coverage closure.
• Own and debug simulation failures; identify and resolve root causes.
• Coordinate with architecture, emulation, silicon bring-up and firmware teams for cross-domain validation and post-silicon activities.

Requirements

Must-have technical skills and experience are listed first; nice-to-have items follow.

• Must-have: Experience in SoC/Subsystem/IP level verification of ARM-based SoCs, including ARM boot sequence knowledge.
• Must-have: Strong knowledge of ARM architecture and AMBA bus standards (AXI-4, CHI, ACE).
• Must-have: Experience with industry-standard interfaces such as DDR, HBM, PCIe, Ethernet and USB.
• Must-have: Hands-on experience coding UVM testbenches, BFMs, monitors and scoreboards; proficient in writing and debugging UVM and C tests.
• Must-have: Proficiency in scripting (tcl, Perl) and familiarity with hardware emulation support.
• Must-have: Familiarity with version control tools (CVS, SVN, GIT).
• Nice-to-have: Exposure to Cadence, Synopsys, Mentor and/or ARM verification tool flows.
• Nice-to-have: Experience with assertion-based formal verification tools and SystemC TLM.
• Nice-to-have: Demonstrated experience leading technical teams or core technical leads.

Education Requirements

Bachelor's degree in Computer Science or Electrical Engineering, or a Master's degree in Computer Science or Electrical Engineering (posting specifies Master's with 8+ years of relevant experience). No other certifications or equivalent-experience language specified.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.