Design Verification Principal Engineer - SoC

Job Title

Design Verification Principal Engineer - SoC

Role Summary

Lead verification for complex SoC projects within the Data Centre Engineering (Compute & Storage) business unit. Responsible for driving verification strategy, execution, and closure across IP, subsystem, and SoC levels.

Work with design, firmware, silicon bring-up and cross-functional teams to ensure functional correctness, performance, and successful tape-out and post-silicon validation.

Experience Level

Senior-level. Requires substantial proven experience in SoC design verification (see Education Requirements for formal degree/experience guidance).

Responsibilities

Primary responsibilities include planning, executing, and closing verification activities for SoC projects.

• Lead end-to-end SoC verification execution and sign-off.
• Define and improve DV processes and methodologies for efficient, high-quality execution.
• Collaborate with IP, subsystem, and SoC teams on test plans, testbench architecture, and milestone reviews.
• Architect and implement simulation testbenches using SystemVerilog/UVM and C.
• Develop and execute verification plans, perform coverage analysis and closure, and run gate-level simulations.
• Debug simulation failures, identify root causes, and drive fixes with design teams.
• Support silicon bring-up and post-silicon validation in partnership with firmware and bring-up teams.
• Use emulation setups to support active debug when required.

Requirements

Must-have technical skills, experience, and attributes.

• Proven experience in verification of Automotive SoCs, ARM-based SoCs, or multimedia SoCs.
• Strong SystemVerilog and UVM expertise and hands-on IP verification experience.
• Excellent debug skills and familiarity with industry-standard DV tools and flows.
• Proficient in C/C++.
• Experience contributing to multiple successful SoC tape-outs in custom silicon or AI/ML product spaces.
• Experience with multi-voltage domain, low-power, and high-performance SoC verification is a plus.
• Exposure to emulation environments for active debug is a plus.
• Strong technical leadership, communication, and ability to multi-task in a fast-paced environment.
• Familiarity with project planning tools.
• Knowledge of Unix/Linux and scripting (shell/perl/python) is a plus.

Education Requirements

BS in Computer Science or Electrical Engineering with 14+ years of relevant experience, or MS with 12+ years of relevant experience. Fields: CS/EE (computer engineering or closely related technical fields). (These degree and experience thresholds were specified in the source.)

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.