Design Verification Principal Engineer - Memory Controller IP

Job Title

Design Verification Principal Engineer - Memory Controller IP

Role Summary

Principal-level verification engineer responsible for defining and driving the verification strategy for memory controller IP. Works with architecture, RTL, validation, and silicon teams to deliver correct, well-tested IP.

Accountable for verification planning, testbench and VIP development, coverage and closure, regressions, and root-cause debug through bring-up. Will mentor engineers and coordinate cross-functional verification activities.

Experience Level

Senior (Principal). Years-of-experience not specified in the source posting.

Responsibilities

The role focuses on ownership of the verification lifecycle for memory controller IP. Key responsibilities include:

• Define and execute verification strategy and plans for memory controller IP (e.g., DDR/LPDDR/HBM as applicable).
• Design, implement, and maintain SystemVerilog/UVM testbenches and verification IP.
• Create directed and constrained-random tests, assertions, and functional coverage models; drive coverage closure.
• Run and manage regression suites, performance/stress tests, and emulation or FPGA prototyping flows.
• Debug RTL/verification failures, analyze root causes, and drive fixes across RTL and verification teams.
• Mentor and lead other verification engineers; coordinate verification tasks with architecture, RTL, firmware, and validation groups.
• Participate in design and verification reviews, and advise on testability and verificationability of RTL designs.

Requirements

Must-have technical skills and experience (summarized):

• Strong experience with SystemVerilog and UVM-based verification methodologies.
• Hands-on experience with memory protocol verification (memory controller, PHY interfaces, DDR/LPDDR/HBM knowledge preferred).
• Proficiency with industry simulators and verification tools (e.g., VCS, Questa, Incisive) and experience with emulation/prototyping flows.
• Experience writing verification scripts and automation using Python, Tcl, or similar scripting languages.
• Proven debugging skills and experience closing coverage and functional bugs to silicon.
• Leadership and mentoring experience, plus strong cross-team communication skills.

Nice-to-have:

• Experience with formal verification, low-power verification techniques, or firmware/bring-up support.
• Experience with hardware-software integration and performance characterization.

Education Requirements

Not specified.

About the Company

Company: Rambus

Headquarters: Sunnyvale, California, USA

Rambus is a global leader in advanced semiconductor and technology solutions, specializing in enhancing data access and improving performance in computing, networking, and storage applications. The company is known for its innovative IP and solutions in memory, security, and interface technologies. With a strong focus on research and development, Rambus continues to push the boundaries of technology to meet the growing demands of the digital age.