Design Verification - Principal Engineer

Job Title

Design Verification - Principal Engineer

Role Summary

Principal-level verification engineer on the Hardware Engineering team tasked with planning and executing SoC/IP verification activities. Focus areas include functional, power-aware, formal, and performance verification for complex semiconductor designs.

Work is based in the Noida engineering organization and involves close collaboration with design, synthesis, and timing teams to achieve verification closure.

Experience Level

Senior / Principal. Posting lists degree-based minimum experience: Bachelor's +8 years, Master's +7 years, or PhD +6 years of relevant hardware engineering experience.

Responsibilities

Primary responsibilities include designing and executing verification strategies, developing verification environments, and driving verification closure.

• Lead functional, power-aware, formal, and performance verification of SoC/IP blocks.
• Develop and maintain UVM/SystemVerilog verification environments and testbenches.
• Perform formal verification using tools such as Jasper or VC Formal, Cadence LEC, or Synopsys Formality.
• Implement and validate UPF/CPF power-intent flows and power-aware verification methodologies.
• Write and debug timing constraints and coordinate with synthesis/timing teams to resolve issues.
• Create verification automation and build flows using Perl/Tcl scripting and makefiles.
• Mentor and guide engineering team members and participate in design and verification reviews.

Requirements

Key technical skills and tools required or strongly preferred.

• Must-have: Deep expertise in functional verification, power-aware verification, formal verification, and performance verification.
• Must-have: Strong hands-on experience with UVM and SystemVerilog.
• Must-have: Experience with formal tools such as Jasper or VC Formal, Cadence LEC, or Synopsys Formality.
• Must-have: Experience with UPF/CPF methodologies and multi-voltage, power-aware flows.
• Must-have: Ability to write and debug timing constraints.
• Must-have: Scripting and automation experience (Perl and/or Tcl, makefile flows).
• Must-have: Familiarity with synthesis-related tools and flows (examples in posting: Synopsys Design Compiler, DCG/DC_NXT/Fusion Compiler, Cadence RC/Genus).
• Nice-to-have: Broad hands-on experience across synthesis, timing, and verification domains and prior mentoring or technical leadership experience.

Education Requirements

Degrees specified in the posting: Bachelor's in Computer Science, Electrical/Electronics Engineering, Engineering, or related field (requires 8+ years experience); OR Master's in those fields (7+ years); OR PhD in those fields (6+ years).

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.