Design Verification Manager

Job Title

Design Verification Manager

Role Summary

Manage and scale a multi-level design verification (DV) team responsible for IP, subsystem and SoC verification for RADAR products. Own verification strategy, methodology, infrastructure and signoff across multiple SoC programs and coordinate with cross-functional teams through silicon bring-up and post-silicon issue resolution.

Experience Level

Senior - typically requires 8+ years of DV experience.

Responsibilities

Lead verification efforts across IP, Subsystem and SoC levels and ensure delivery from specification through post-silicon verification and customer issue resolution.

• Recruit, mentor and grow a high-performing verification team across IP/Subsystem/SoC domains.
• Define and drive verification strategy, plans and signoff criteria to achieve spec-to-regression traceability and coverage goals.
• Own DV environment development and maintenance: testbenches, checkers, coverage monitors and DV flow updates.
• Coordinate verification activities with Architecture, RTL, PD, DFT, Systems, Analog, Firmware and applications teams.
• Lead regression campaigns and final SoC DV signoff using C and/or SystemVerilog-UVM methodologies, adhering to functional-safety guidelines.
• Participate in customer reviews and certification activities (e.g., ISO26262, ISO21434) and support post-silicon debug and issue resolution.

Requirements

Must-have technical skills and experience for immediate contribution.

• 8+ years of design verification experience for IP, subsystem and SoC, including post-silicon validation.
• Proven people management and project leadership experience in DV programs.
• Deep knowledge of UVM/SystemVerilog, functional verification methodologies and coverage-driven verification.
• Experience with C-based SoC verification and firmware-in-the-loop verification scenarios.
• Familiarity with RTL simulation modes (GLS/PAGLS) and regression/coverage signoff processes.
• Strong debug skills with Verilog/VHDL and understanding of digital design fundamentals, computer architecture and bus protocols.
• Experience working with cross-functional teams for first-pass silicon success and post-silicon closure.

Nice-to-have skills:

• Scripting for DV (Python, Perl) or ML-assisted verification flows.
• Experience with Cadence toolchain (Xcelium, vManager, Formal, safety simulators) or equivalent tools.
• Knowledge of AMS, CDC verification, formal methods and DFT.
• Familiarity with functional safety and cybersecurity processes (ISO26262, ISO21434).

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Electronics / Communication Engineering, Computer Science, or a related technical field is expected (as stated in the posting).

About the Company

Company: Texas Instruments

Headquarters: Dallas, Texas, USA

Texas Instruments is a global semiconductor company that designs, manufactures, and sells analog and embedded processing chips for various markets including industrial, automotive, and personal electronics. The company's innovations aim to make electronics more affordable and reliable, fostering advancements in technology through each generation of semiconductors.