Design Verification Engineer to Staff Engineer (Unit Level Test)
The Design Verification Engineer will collaborate with CPU designers, compiler teams, and system verification teams to generate automated test cases. The primary mission is to establish a highly scalable and reusable constrained random test bench that produces coverage driven tests.
Mid-level, with at least 3 years of relevant experience.
The key responsibilities for this role include:
Applicants must meet the following requirements:
Not specified.
Company: SiFive
Headquarters: San Mateo, California, United States
SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.
