Design Verification Engineer to Staff Engineer (Unit Level Test)
SiFiveJob Title
Design Verification Engineer to Staff Engineer (Unit Level Test)
Role Summary
The engineer will design and implement coverage-driven verification for CPU/memory subsystem and interconnect units. Work with CPU designers, compiler, performance and system verification teams to generate automated tests and build a scalable, reusable constrained-random testbench.
Experience Level
Senior role (Staff Engineer level). The posting requests at least 3+ years of recent verification experience.
Responsibilities
Primary responsibilities focus on unit-level verification for memory subsystem and interconnect components.
- Review product specs from a verification perspective and collaborate on feature specs, test plans, and failure analysis.
- Design and implement checkers and assertions for memory subsystem and interconnect designs.
- Develop testbenches, verification IP (VIP), tools and test suites using UVM, C/C++, or other required languages.
- Generate coverage-driven tests and write functional coverage; analyze code and functional coverage and close coverage holes.
- Debug failures, perform root-cause analysis, and work with designers to resolve issues.
Requirements
Must-have skills and experience required for this position; nice-to-have items are listed separately.
- At least 3+ years of recent experience with verification tools and methodologies: SystemVerilog/UVM, Verilog, Verdi/DVE, Makefiles, and scripting languages.
- Experience developing and maintaining verification IP and constrained-random UVM testbenches.
- Proven ability to write functional coverage, analyze coverage metrics, and close coverage gaps.
- Experience developing checkers, assertions, and test suites for memory/interconnect subsystems.
- Strong troubleshooting and analytical skills; experience in failure analysis and root-cause debugging.
- Good interpersonal and communication skills to collaborate across design, compiler, performance, and system verification teams.
- Nice-to-have: Familiarity with AMBA protocols and prior exposure to processor or SoC architecture.
Education Requirements
Not specified.
About the Company
Company: SiFive
Headquarters: San Mateo, California, United States
SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.
