Design Verification Engineer to Staff Engineer (Unit-Level Test)

Job Title

Design Verification Engineer to Staff Engineer (Unit-Level Test)

Role Summary

Work with CPU designers, compiler, performance, and system verification teams to automatically generate test cases and verification assets that meet cross-team requirements. The role focuses on establishing a scalable, reusable constrained-random testbench and coverage-driven test suites for unit-level verification.

Primary scope includes memory subsystem and interconnect verification, testbench and tool development, coverage closure, and failure analysis in collaboration with design teams.

Experience Level

Senior. The posting requests at least 3+ years of recent experience with standard verification tools and methodologies; senior technical responsibility is expected given the "Staff" designation in the title.

Responsibilities

Key responsibilities include:

• Review and influence product definitions and specifications from a verification perspective; collaborate on feature specifications and test plans.
• Develop checkers and assertions to verify memory subsystem designs including interconnects.
• Design and implement tools, testbenches, and test suites (UVM, C/C++, or other as required) to execute verification plans.
• Develop and maintain in-house Verification IP (VIP) for memory subsystem and interconnect testing.
• Create functional coverage models, analyze code and functional coverage, and drive coverage closure.
• Perform failure analysis and work with design teams to debug and resolve issues.

Requirements

Must-have and preferred qualifications:

• Must-have: 3+ years recent experience with verification tools and methodologies (SystemVerilog/UVM, Verilog, Verdi/DVE, Makefiles, scripting languages).
• Must-have: Thorough understanding of verification flow: test-plan generation, test generation, failure analysis, coverage analysis and closure.
• Must-have: Proficient troubleshooting and strong analytical skills; effective interpersonal and collaboration skills.
• Preferred / Nice-to-have: Familiarity with AMBA protocols.
• Preferred / Nice-to-have: Solid understanding of processor and SoC architecture, or a strong desire and ability to learn these areas quickly.
• Preferred: Experience developing VIP for memory subsystems and interconnects.

Education Requirements

Not specified.

About the Company

Company: SiFive

Headquarters: San Mateo, California, United States

SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.