Design Verification Engineer to Staff Engineer (Unit-Level Test)

Job Title

Design Verification Engineer to Staff Engineer (Unit-Level Test)

Role Summary

Work with CPU designers, compiler, performance and system verification teams to generate automated, coverage-driven unit-level tests and to establish a scalable, reusable constrained-random verification environment for memory subsystem and interconnect validation.

Experience Level

Senior / Staff-level role. The posting requests at least 3+ years of recent verification experience; the title indicates a senior/staff position.

Responsibilities

Deliver verification infrastructure, test suites and coverage closure for unit-level memory subsystem and interconnect verification.

• Collaborate with design and system teams to influence product specifications, define test plans, and perform failure analysis.
• Design and implement checkers and assertions for memory subsystem and interconnect designs.
• Develop and maintain UVM testbenches, Verification IP (VIP), and test suites; create tools and harnesses as needed (C/C++, scripting, etc.).
• Generate automated, coverage-driven tests and close functional and code coverage gaps.
• Perform debugging, root-cause analysis, and verification closure activities.

Requirements

Key qualifications and skills required for success in this role.

• Minimum 3+ years recent experience with standard verification tools and methodologies: SystemVerilog/UVM, Verilog, Verdi/DVE, Makefiles, and scripting.
• Proven experience developing UVM testbenches, checkers, assertions, and in-house VIP.
• Strong understanding of verification flow: test plan generation, test generation, failure analysis, coverage analysis and closure.
• Experience writing functional coverage, analyzing code and functional coverage, and closing coverage holes.
• Proficient troubleshooting and strong analytical skills.
• Good interpersonal and communication skills for cross-discipline collaboration.
• Solid understanding of processor and SoC architecture, or a demonstrated ability to learn these quickly.
• Nice-to-have: Familiarity with AMBA protocols.

Education Requirements

Not specified.

About the Company

Company: SiFive

Headquarters: San Mateo, California, United States

SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.