Marvell Technology logo

Design Verification Engineer, Staff

Marvell Technology
June 29, 2026
Full-time
On-site
Santa Clara, California, United States
$96,570 - $144,600 USD yearly
Verification Jobs, Level - Senior

Job Title

Design Verification Engineer, Staff

Role Summary

Staff design verification engineer responsible for functional verification of ASIC blocks. Work on verification of high-speed data-transfer designs for enterprise, cloud/AI, carrier and automotive customers.

This is an in-office position on the Design Verification Team in Santa Clara collaborating closely with RTL and DFT engineers to deliver verified silicon blocks.

Experience Level

Senior (Staff). The posting describes candidates with approximately 2–3 years of professional experience if holding a Bachelor's degree; advanced degrees (Master's/PhD) are also acceptable.

Responsibilities

Primary day-to-day responsibilities include simulation-driven verification, debugging, and coordination with design teams.

  • Create and maintain SystemVerilog testbenches and verification environments.
  • Run simulations (Synopsys VCS or equivalent) and debug RTL with RTL engineers until design meets specifications.
  • Collaborate with DFT engineers to ensure testability and resolve integration issues.
  • Track verification status, attend staff meetings, and present test plans and schedules for larger blocks.
  • Iterate tests and fixes through multiple design cycles to achieve required quality.
  • Write scripts to automate verification tasks and analyses.

Requirements

Must-have technical skills, tools, and behaviors.

  • Practical experience developing and debugging SystemVerilog testbenches and verification code.
  • Experience running simulations with Synopsys VCS or similar EDA simulators.
  • Comfortable working in a Linux environment and scripting with Python to automate tasks.
  • Strong attention to detail and persistence in iterating designs to closure.
  • Good communication and teamwork skills; able to report status and escalate issues.
  • Ability to present verification strategy and progress to review committees.
  • Nice-to-have: experience with Cadence or Mentor tools, DFT integration experience, and verification of high-speed interfaces or automotive/telecom applications.

Education Requirements

Required: Bachelor’s degree in Electrical Engineering or Computer Engineering plus 2–3 years of related professional experience, OR a Master’s degree or PhD in Electrical Engineering or Computer Engineering. Relevant coursework or background should include analog classes, Verilog or VHDL, basic circuits, computer architecture, and a focus or projects in VLSI/chip design.


About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.

Marvell Technology logo

Date Posted: 2026-06-26