Design Verification Engineer, Staff
Staff design verification engineer responsible for functional verification of ASIC blocks. Work on verification of high-speed data-transfer designs for enterprise, cloud/AI, carrier and automotive customers.
This is an in-office position on the Design Verification Team in Santa Clara collaborating closely with RTL and DFT engineers to deliver verified silicon blocks.
Senior (Staff). The posting describes candidates with approximately 2–3 years of professional experience if holding a Bachelor's degree; advanced degrees (Master's/PhD) are also acceptable.
Primary day-to-day responsibilities include simulation-driven verification, debugging, and coordination with design teams.
Must-have technical skills, tools, and behaviors.
Required: Bachelor’s degree in Electrical Engineering or Computer Engineering plus 2–3 years of related professional experience, OR a Master’s degree or PhD in Electrical Engineering or Computer Engineering. Relevant coursework or background should include analog classes, Verilog or VHDL, basic circuits, computer architecture, and a focus or projects in VLSI/chip design.
Company: Marvell Technology
Headquarters: Santa Clara, California, United States
Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.
