Design Verification Engineer — Memory Subsystem

Job Title

Design Verification Engineer — Memory Subsystem

Role Summary

Join the memory subsystem verification team to develop and execute verification strategies for high-performance memory subsystems, including memory controllers, PHY interfaces, and protocols such as DDR/LPDDR/HBM. The role covers the full verification lifecycle: planning, building UVM-based testbenches, assertion development, simulation, debugging, and driving coverage closure.

Experience Level

Mid-level — typically 3–10 years of ASIC/SoC/IP or subsystem design verification experience.

Responsibilities

Accountable for planning, implementing, and verifying complex memory-related RTL and supporting cross-team integration and debug activities.

• Define verification strategies, test plans, and coverage goals for memory subsystem designs.
• Build, enhance, and maintain reusable SystemVerilog/UVM verification environments and formal flows.
• Develop UVM components: sequences, drivers, monitors, scoreboards, agents, environments, and reference models.
• Create and run constrained-random, directed, error-injection, and corner-case tests.
• Write and maintain SystemVerilog Assertions for protocol, timing, and functional checks.
• Verify memory-controller, PHY-interface, and memory-subsystem behavior across operating modes.
• Analyze simulation failures with waveform viewers, logs, and transaction databases; perform root-cause analysis and drive fixes with RTL/architecture teams.
• Support regression execution, failure triage/classification, and functional/code/coverage closure reporting.
• Collaborate with architecture, design, physical design, firmware, modeling, and system validation teams.

Requirements

Must-have technical skills and experience required to perform the role.

• 3–10 years of experience in ASIC, SoC, IP, or subsystem design verification.
• Strong hands-on experience with Verilog and SystemVerilog.
• Practical experience with UVM and building reusable UVM-based verification environments.
• Proficiency writing SystemVerilog Assertions and using assertion-based verification.
• Experience developing UVM components (sequences, drivers, monitors, scoreboards) and functional coverage models.
• Experience with constrained-random and coverage-driven verification methodologies.
• Solid understanding of digital design and verification fundamentals: clocking, reset, synchronous/asynchronous logic, and multi-clock-domain designs.
• Experience with simulation-based verification, waveform analysis, regression execution, and failure debug.
• Strong analytical, problem-solving, communication, and collaboration skills.

Nice-to-have (preferred):

• Experience verifying LPDDR/DDR/HBM, DDR PHYs, or custom memory interfaces and familiarity with JEDEC specifications.
• Experience integrating verification IP and using memory models.
• Power-aware simulation experience (UPF), formal verification, or assertion-based methodologies.
• Knowledge of standard interfaces (AXI, APB, AHB, DFI) and performance verification (bandwidth, latency, QoS).
• Experience with memory training, initialization, refresh, power management, calibration, and error-handling scenarios.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field; PhD also acceptable. The posting specifies typical minimum combinations: Bachelor's degree plus 2+ years of ASIC/verification-related experience, OR Master's degree plus 1+ year of related experience, OR PhD in a relevant field.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.