Design Verification Engineer IV
eInfochipsJob Title
Design Verification Engineer IV
Role Summary
Senior verification engineer responsible for architecting and executing ASIC SoC verification environments from verification plan through multi-million gate tapeout. The role combines SystemVerilog/UVM environment development, SoC test firmware development, formal verification integration, and automation to ensure feature coverage and regression stability.
Experience Level
Senior. Typical background: minimum 8 years related experience with a 4-year degree, or 6 years with an advanced degree, or equivalent practical experience.
Responsibilities
Primary responsibilities focus on verification architecture, environment development, test development, and delivery for ASIC SoC projects.
- Architect and implement SystemVerilog/UVM verification environments for SoC components and interconnects.
- Define verification plans and drive regression and coverage closure to meet tapeout objectives.
- Develop complex self-checking testbenches with constrained-random stimulus and coverage models.
- Architect SoC test firmware, create test plans, and develop/debug platform tests in C/C++.
- Integrate and maintain end-to-end formal verification flows and create assertions/assumptions/cover properties.
- Automate verification tasks by developing and modifying scripts and tooling.
- Review functional and technical specifications and contribute to verification methodology development.
- Mentor junior engineers and lead project-level verification activities; work independently with minimal supervision.
Requirements
Must-have technical skills and experience; concise list of required capabilities.
- Strong SystemVerilog and UVM expertise.
- Experience with interconnects and interfaces: AXI, on-chip networks (NOC), Ethernet, PCIe, UCIe or similar switch fabrics.
- Experience with CPU subsystems (ARM or RISC-V) and firmware-level C development for SoC tests.
- Proven track record of regression management and coverage closure on complex designs.
- Experience developing self-checking testbenches and coverage-driven verification.
- Familiarity with formal verification objectives and integrating formal tools into flows.
- Scripting and automation skills (e.g., Python, Perl, shell) to support verification flows.
- Strong debugging skills for SoC bring-up and platform-level issues; ability to work onsite in San Jose, CA.
Nice-to-have: experience leading verification teams, methodology contributions, prior multi-million gate tapeout experience.
Education Requirements
Typical requirement is a 4-year bachelor's degree or equivalent; an advanced degree may reduce the years of experience required. The posting allows equivalent practical experience in lieu of a degree. No specific fields of study were specified.
About the Company
Company: eInfochips
Headquarters: Bengaluru, India
eInfochips is a product engineering and semiconductor design services company offering embedded software, SoC design and verification, testing, and IoT solutions. It operates as part of Arrow Electronics, serving clients across industries worldwide.
